As fault handling in multi-processor system-on-chips (MPSoCs) is a major challenge, we have developed an MPSoC demonstrator that enables experimentation on fault injection and fault handling. Our MPSoC demonstrator consists of (1) an MPSoC model with a set of components (devices) each equipped with fault detection features, so called instruments, (2) an Instrument Access Infrastructure (IAI) based on IEEE P1687 that connects the instruments, (3) a Fault Indication and Propagation Infrastructure (FIPI) that propagates fault indications to system-level, (4) a Resource Manager (RM) to schedule jobs based on fault statuses, (5) an Instrument Manager (IM) connecting the IAI and the RM, and (6) a Fault Injection Manager (FIM) that inserts faults. The main goal of the demonstrator is to enable experimentation on different fault handling solutions. The novelty in this particular demonstrator is that it uses the existing test features, i.e. IEEE P1687 infrastructure, to assist fault handling. The demonstrator is implemented and a case study is performed.

It is common to embed instruments when developing integrated circuits (ICs). These instruments are accessed at post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and operator-driven in-field test. At any of these scenarios, it is of interest to access some but not all of the instruments. IEEE 1149.1-2013 and IEEE 1687 propose Test Access Port based (TAP-based) mechanisms to design flexible scan networks such that any combination of instruments can be accessed from outside of the IC. Previous works optimize TAP-based scan networks for one scenario with a known number of accesses. However, at design time, it is difficult to foresee all needed scenarios and the exact number of accesses to instruments. Moreover, the number of accesses might change due to late design changes, addition/exclusion of tests, and changes of constraints. In this paper, we analyze and compare seven IEEE 1687 compatible network design approaches in terms of instrument access time, hardware overhead, and robustness. Given the similarities between IEEE 1149.1-2013 and IEEE 1687, the conclusions are also applicable to IEEE 1149.1-2013 networks.

The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic (instruments), such as scan chains and temperature sensors. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan path to allow flexibility both in designing the instrument access network and in scheduling the access to instruments. This paper presents algorithms to compute the overall access time (OAT) for a given P1687 network. The algorithms are based on analysis for flat and hierarchical network architectures, considering two access schedules, i.e., concurrent schedule and sequential schedule. In the analysis, two types of overhead are identified, i.e., network configuration data overhead and JTAG protocol overhead. The algorithms are implemented and employed in a parametric analysis and in experiments on realistic industrial designs.

In contrast to IEEE 1149.1, IEEE P1687 allows, through segment insertion bits, flexible scan paths for accessing on-chip instruments, such as test, debug, monitoring, measurement and configuration features. Flexible access to embedded instruments allows test time reduction, which is important at production test. However, the test access scheme should be carefully selected such that resource constraints are not violated and power constraints are met. For IEEE P1687, we detail in this paper session-based and session-less test scheduling, and propose resource and power-aware test scheduling algorithms for the detailed scheduling types. Results using the implementation of our algorithms shows on ITC'02-based benchmarks significant test time reductions when compared to non-optimized test schedules.

The IEEE P1687 (IJTAG) standard proposal aims at standardizing the access to embedded test and debug logic (instruments) via the JTAG TAP. P1687 specifies a component called Segment Insertion Bit (SIB) which makes it possible to construct a multitude of alternative P1687 instrument access networks for a given set of instruments. Finding the best access network with respect to instrument access time and the number of SIBs is a time-consuming task in the absence of EDA support. This paper is the first to describe a P1687 design automation tool which constructs and optimizes P1687 networks. Our EDA tool, called PACT, considers the concurrent and sequential access schedule types, and is demonstrated in experiments on industrial SOCs, reporting total access time and average access time.

Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor technologies require not only manufacturing test, but also in-field test. Preferably, the same test set is utilized both at manufacturing test and in-field test. While deterministic test patterns provide high fault coverage, storing complete test vectors leads to huge memory requirements and inflexibility in applying tests. In an IEEE 1149.1 (Boundary scan) environment, this paper presents an approach to efficiently embed deterministic test patterns in the system by taking structural information of the system into account. Instead of storing complete test vectors, the approach stores only commands and component-specific test sets per each unique component. Given a command, test vectors are created by a test controller during test application. The approach is validated on hardware and experiments on ITC'02 benchmarks and industrial circuits show that the memory requirement for storing the test data for a system is highly related to the number of unique components.

The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.

Integrated circuits, printed circuits boards, and multi-board systems are becoming increasingly complex to test. A major obstacle is test access, which would be eased by effective standards for the communication between devices-under-test (DUTs) and the test manager. Currently, the Internal Joint Test Access Group (IJTAG) work at micro-level on a standard for interfacing embedded on-chip instruments while the System JTAG (SJTAG) work at macro-level on a standard for system-level test management that connects IJTAG compatible instruments with the system test manager. In this paper we discuss requirements on a test protocol to be used in an SJTAG/ IJTAG environment. We have from a number of use scenarios made an analysis and defined protocol requirements. We have taken the Standard Test and Programming Language (STAPL), which is built around a player (interpreter), and defined required extensions. The extensions have been implemented in an extended version of STAPL and we have made experiments with a PC acting as test controller and an FPGA being the DUT.

The backplane in a multi-board system has a limited wiring capability, which makes additional backplane boundary-scan wiring to link the boards highly costly. The problem is to access the boundary-scan tested boards with the boundary-scan controller at the central board. In this paper we propose an approach suitable for the advanced telecom computing architecture standard where we make use of the existing I2C-bus and the intelligent platform management bus (IPMB) protocol for application of operational tests. We have defined a protocol with commands and responses as well as a test data format for storing test data on the boards to support the remote execution of boundary-scan tests. For validation of the proposed approach we have developed a demonstrator

This article provides an overview on SoC's on board testing. It discusses the topic of life cycle perspective, efficient test required, re-use challenges, test access and control, SoC DFT architecture, test sequencing, DFT support, and debug and diagnosis support.

This article provides an overview on SoC's on board testing. It discusses the topic of life cycle perspective, efficient test required, re-use challenges, test access and control, SoC DFT architecture, test sequencing, DFT support, and debug and diagnosis support

We present two novel Locally Optimal Routing Algorithms (LORA) for ad hoc mobile wireless networks with fast changing topology. Instead of modifying globally optimal shortest path routing algorithms, we propose two new algorithms that are designed to match the characteristics of wireless physical channels in a network with dynamic ad hoc topology and mobile users. Motivated by practical constraints, we design LORA to be simple to implement at each node, requiring very low computational load and a small amount of memory, and can provide fast rerouting under distributed control when nodes or links fail. The first algorithm, LORA1, is designed for networks with slowly moving users, using a new random graphical model and randomized algorithms. The second algorithm, LORA2, is designed for fast moving users, building upon LORA1 with an additional mobility diversity feature. Various properties of the algorithms are tested by simulations. Analytic results bound the performances of LORA. We also outline several extensions of LORA.

We present two novel Locally Optimal Routing Algorithms (LORA) for ad hoc mobile wireless networks with fast changing topology. Instead of modifying globally optimal shortest path routing algorithms, we propose two new algorithms that are designed to match the characterisitics of wireless physical channels in a network with dynamic ad hoc topology and mobile users. Motivated by practical constraints, we design LORA to be simple to implement at each node, requiring very low computational load and a small amount of memory, and can provide fast rerouting under distributed control when nodes or links fail. The first algorithm, LORAl, is designed for networks with slowly moving users, using a new random graphical model and randomized algorithms. The second algorithm, LORAB, is designed for fast moving users, building upon LORAl with an additional mobility diversity feature. Various properties of the algorithms are tested by simulations. Analytic results bound the performances of LORA. We also outline several extensions of LORA.

For ad hoc wireless mobile networks, we present several criteria and algorithms to control the admission of new transceivers and to balance the tradeoff between power consumption and link maintenance. From a random graph theoretic perspective, we first propose an admission control scheme based on the evolution of ad hoc networks. This also provides analyses on QoS assurance and pricing schemes. For the power control problem, based on thresholding phenomena in random graph models, we balance power conservation and interference mitigation with network performance criteria such as robust routing, multicasting, transmission delay and length of multi-hop transmissions.

We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.