Future CPU directions are increasingly emphasizing parallel compute platforms which are critically dependent upon upon greater core to core communication as well as generally stressing the overall memory and storage interconnect hierarchy to a much greater degree than extrapolations of past platform needs. Performance is critically dependent upon memory bandwidth and latency but must be moderated with power and cost considerations. 3D stacking of CPU's and memory (i.e. a last level cache) is a potential solution that provides the necessary bandwidth within a reasonable power envelope.

Moore’s law has been a foundation of modern electronics, sustained primarily by scaling. But can this continue despite the serious problems of litho, variability, device physics, and cost? This panel looks at several possibilities. Perhaps Moore’s law will muddle through, as it has so far, with a combination of tools, process, and design. But even if technically possible, Moore’s law is in practice driven by economics, and economics might turn against further scaling. Also, we’ve all seen how performance of single cores has topped out, despite scaling. Might this be a fundamental problem with planar technologies, prompting the need to go 3-D to get further performance increases? Or might CMOS itself give way to other technologies, allowing Moore’s law yet another respite? Compare and contrast for yourself these four very different visions of the future of your job, your industry, and your personal gadgets.