Demo Data from SIGIR 2026 / reviewers in the wild / expert
Johann Deneux
dblp:76/2580
· DBLP profile ↗
5ranked-venue papers
0as first author
0since 2021 · last 2008
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Theory of computation · 4Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
2 papers |
Automata and formal languages · 54% Automated reasoning and model checking · 46% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Automata and formal languages
decidability and complexity |
0.1 | 1 | 2005 | Decidability and Complexity Results for Timed Automata via Channel Machines · ICALP 2005 |
Automata and formal languages
timed automata |
0.1 | 1 | 2005 | Decidability and Complexity Results for Timed Automata via Channel Machines · ICALP 2005 |
Automated reasoning and model checking › model checking
infinite-state model checking |
0.0 | 1 | 2004 | Multi-Clock Timed Networks · LICS 2004 |
Automated reasoning and model checking
safety verification |
0.0 | 1 | 2004 | Multi-Clock Timed Networks · LICS 2004 |
Methods — techniques the papers use, named apart from their topics
reduction · 0.1channel machines · 0.1parameterized verification · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2008 | Universality Analysis for One-Clock Timed Automata
Parosh Aziz Abdulla, Johann Deneux, Joël Ouaknine, Karin Quaas, James Worrell 0001 |
Fundam. Informaticae | 2 |
| 2005 | Decidability and Complexity Results for Timed Automata via Channel Machines
Parosh Aziz Abdulla, Johann Deneux, Joël Ouaknine, James Worrell 0001 |
ICALP | 2 |
| 2005 | Minimization of Non-deterministic Automata with Large Alphabets
Parosh Aziz Abdulla, Johann Deneux, Lisa Kaati, Marcus Nilsson |
CIAA | 2 |
| 2004 | Designing Safe, Reliable Systems Using Scade
Parosh Aziz Abdulla, Johann Deneux, Gunnar Stålmarck, Herman Ågren, Ove Åkerlund |
ISoLA | 2 |
| 2004 | Multi-Clock Timed NetworksabstractWe consider verification of safety properties for parameterized systems of timed processes, so called timed networks. A timed network consists of a finite state process, called a controller, and an arbitrary set of identical timed processes. In a previous work, we showed that checking safety properties is decidable in the case where each timed process is equipped with a single real-valued clock. It was left open whether the result could be extended to multi-clock timed networks. We show that the problem becomes undecidable when each timed process has two clocks. On the other hand, we show that the problem is decidable when clocks range over a discrete time domain. This decidability result holds when processes have any finite number of clocks. Parosh Aziz Abdulla, Johann Deneux, Pritha Mahata |
LICS | 2 |