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Darshan Desai

dblp:76/3975 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 77% Processor architecture and microarchitecture · 12% Memory systems · 12%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
benchmarking		 0.112007
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture · SIGMETRICS 2007
Performance modeling and evaluation › system-level analysis › architecture evaluation
processor performance characterization		 0.112007
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture · SIGMETRICS 2007
Processor architecture and microarchitecture
branch prediction		 0.012007
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture · SIGMETRICS 2007
Memory systems
cache		 0.012007
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture · SIGMETRICS 2007

Methods — techniques the papers use, named apart from their topics

workload characterization · 0.1IPC analysis · 0.1
YearPublicationVenuePosition
2007 Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture
abstract
Recently SPEC1 released the next generation of its CPU benchmark, widely used by compiler writers and architects for measuring processor performance. This calls for characterization of the applications in SPEC CPU2006 to guide the design of future microprocessors. In addition, it necessitates assessing the change in the characteristics of the applications from one suite to another. Although similar studies using the retired SPEC CPU benchmark suites have been done in the past, to the best of our knowledge, a thorough characterization of CPU2006 and its comparison with CPU2000 has not been done so far. In this paper, we present the above; specifically, we analyze IPC (instructions per cycle), L1, L2 data cache misses and branch prediction, especially in CPU2006.
Arun Kejariwal, Gerolf Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum
 SIGMETRICS3