A complete thermal energy harvesting power supply for implantable pacemakers is presented in this paper. The designed power supply includes an internal startup and does not need any external reference voltage. The startup circuit includes a prestartup charge pump (CP) and a startup boost converter. The prestartup CP consists of an ultralow-voltage oscillator followed by a high-efficiency modified Dickson. Forward body biasing is used to effectively reduce the MOS threshold voltages as well as the supply voltage in oscillator and CP. The steady-state circuit includes a high-efficiency boost converter that utilizes a modified maximum powerpoint tracking scheme. The system is designed so that no failure occurs under overload conditions. Using this approach, a thermal energy harvesting power supply has been designed using 180-nm CMOS technology. According to HSPICE simulation results, the circuit operates from input voltages as low as 40 mV provided from a thermoelectric generator and generates output voltages up to 3 V. A maximum power of 130 μW can be obtained from the output of the boost converter, which means that its efficiency is 60%. A minimum voltage of 60 mV and a maximum time of 400 ms are needed for the circuit to start up.

This paper presents an accurate analytical compact model for Schottky-barrier-type graphene nanoribbon field-effect transistors (SB-GNRFETs). This is a physics-based analytical model for the current-voltage (I-V) characteristics of SB-GNRFETs. The proposed model considers various design parameters and process variation effects, including graphene-specific line-edge roughness, which allows thorough exploration and evaluation of SB-GNRFET circuits. We develop accurate approximations of SB tunneling, channel charge, and current, which provide accurate results while maintaining model compactness. We evaluate the effect of design parameters and process variations on the performance of SB-GNRFETs. We also compare circuit-level performance of SB-GNRFETs with multigate (MG) Si-CMOS (e.g., FinFETs). Our circuit simulations indicate that SB-GNRFET has an energy-delay product (EDP) advantage over Si-CMOS, although GNR-specific process variation, especially the line-edge roughness, would significantly downgrade such an advantage; the EDP of the ideal SB-GNRFET (assuming no process variation) is ~2.5% of that of Si-CMOS, while the EDP of the nonideal case with process variation is ~68% of that of Si-CMOS. Finally, we study technology scaling with SB-GNRFET and MG Si-CMOS. We show that the EDP of ideal (nonideal) SB-GNRFET is ~0.88% (54%) EDP of that of Si-CMOS as the technology nodes scale down to 7 nm.

In this paper, a new method is presented to calculate the exact analytical solution of distributed RC, LC, and RLC interconnects with a random input at an arbitrary point through the line. The proposed method, based on a modified Duhamel theorem, is used to calculate the time-domain transient response of the initially conditioned interconnects. This method is applied to a line driven by ramp and exponential inputs. The new analytical solutions are expressed as an infinite summation of sinusoidal terms. However, a negligible worst case error of <;1% is observed for the expressions compared with HSPICE simulations for Fourier series with tens of terms. In addition, from these results a new model for transient response of a line considering the driver output resistance and capacitance is presented. Good accuracy is observed between the model and HSPICE simulations for various distributed interconnects and drivers. Furthermore, the developed solution is extended to include signal transient and crosstalk noise in multicoupled inductive-effect-prominent lines. In addition, arbitrary switching patterns for identical and nonidentical lines are investigated employing the new method and evaluated with HSPICE simulations.

This paper presents an off-line interconnect test methodology that implements the MDSI (Maximal Dominant Signal Integrity) crosstalk fault model. The test methodology consists of MDSI test pattern generators and response analyzers that are incorporated into the IEEE BS 1149.1 Standard on the two sides of an interconnect. This work is the first in implementing MDSI hardware structure. Our method is compared with hardware structures implementing MA interconnect tests.

In this brief, a novel methodology for the prediction of three phenomena related to the interconnects in VLSI circuits will be presented. First, the power (including crosstalk-induced power) prediction for ultradeep submicron ICs and nano systems is proposed. The novelty of the method for crosstalk prediction is deduced by employing a polynomial progressive calibration. Second, as a part of this methodology, we present a new solution for power prediction of through-silicon-vias.

With Fourier series and Fourier integrals, a new and systematic approach, called the Amir and Nasser (AMN) method, is proposed to derive exact analytical expressions for step input response of distributed resistance capacitance (RC), inductance-capacitance (LC), and resistance-inductance-capacitance (RLC) models of interconnects. These solutions are obtained for time-domain responses of any arbitrary point on a finite interconnect line, considering initial voltage through the line. This method is appropriate for both on-chip and printed circuit board wires without any limitations in their length or characteristic parameters. The developed solutions are expressed as infinite summation of sinusoidal terms. An accuracy of over 99.5% is observed for the expressions compared with the HSPICE simulations for at most a number of several tens of sinusoidal terms for Fourier series. It is shown that ignoring the initial voltage through the line leads to considerable error as high as 33% at the far end voltage in global interconnects for 65-nm technology node. The AMN method is extended to semi-infinite distributed RC and RLC interconnects for which exact closed-form expressions are achieved.

In this brief, we use the alpha power law model for MOS devices to reach a more accurate modeling of CMOS buffers in very deep submicrometer technologies. We derive alpha model parameters of a CMOS buffer for 90-, 65-, and 45-nm technologies using HSPICE simulations. By analytical efforts we find the output resistance of a minimum-size buffer and compare it with those extracted from HSPICE simulations. We propose a new model for the output resistance of a given-size buffer in any technology, which demonstrates 3% error on average as opposed to the conventional model. Also a new buffer resistance is proposed analytically and numerically to calculate the crosstalk for interconnect analysis applications. In addition, we propose a model for the transfer function zero generated by the gate-drain capacitances of MOS transistors, which cause the overshooting effect, and develop an accurate expression for modeling this phenomenon. As the final point, together with the input-to-output capacitance, the equivalent output resistors present a simple and accurate macromodel for the CMOS buffer.

In this paper we propose an accurate and predictive interconnect density function (PIDF) for very deep submicrometer (VDSM) integrated circuits and nano-systems using continuous stochastic functions. PIDF is the core of an interconnect-centric prediction engine, named ICPEn, which gets its input parameters from the design flow of conventional chips, VDSM ICs, and/or nano-systems. Initially layout information is not necessary for PIDF to function properly. In average, we show that PIDF presents at least 10 times more accuracy than previous works using the real data. Moreover, PIDF enables ICPEn to predict the power, the delay, and the crosstalk. Credibility and accuracy of the last three predictions are proven using several standard ISCAS benchmarks and layouts. Using PIDF we extract a safe operating space (SOS) needed for the interconnect-centric design flow where the delay and the power boundary compliance are essential needs in any early design stages of ultra dense ICs. Based on the use of central limit theorem, the other novelty of PIDF is that the statistical distribution employed for the prediction of interconnect density function tends toward a continuous normal distribution which minimizes the residual error of the prediction and verifies the effectiveness of PIDF.

In this article, a novel model of phase noise in electrical oscillators is presented. This model is based on frequency modulation (FM). The proposed model shows physically and mathematically the effect of oscillator waveform, oscillation frequency and the swing voltage of output waveform on the phase noise. This model also explains why ring oscillators have larger phase noise in compare to sinusoidal oscillators, which the previous models could not model it completely. Using this model enables us to define some rules to design a low phase noise oscillator

A 5.25-GHz low noise amplifier (LNA), has been proposed for use in a receiver architecture for IEEE 802.16a WMAN. The targeted frequency band is the unlicensed band UN11 5 GHz. The amplifier has been simulated with two different spiral inductor models as Ld. In our spiral inductor model we have improved "the Greenhouse spiral inductor model", then we compare the results with the case when we use the spiral inductor model of the technology. The amplifier achieves voltage gain of 16.4, 19.4 dB with a noise figure of only 1.5, 1.58 dB, the IIP3is 14, 13.1-dBm and the reverse isolation is about -10.7, -13.2 dB for our spiral inductor model and that of technology, respectively. Using a 0.18 mum CMOS process, the LNA dissipates 7.2 mW from a 1.8 V supply voltage in both cases. In this paper, we present an analysis of the LNA architecture

Two parameters that contribute significantly in a CMOS inverter delay are the output load and propagation of the control signal across the gates of its transistors. The latter one which is due to the polysilicide gate resistance (PGR) is proportional to the gate width, W. The PGR effect causes the inverter transistors remain simultaneously on, for further time in the saturation region during transient instants, so that the short circuit power consumption increases largely. In this paper, we model the PGR resistance effect using the distributed RC approach based on a new proposed technique. Additionally, in order to reduce its negative impact on the circuit performance, we utilize a relevant optimized branching method. The results obtained from our model compared to the HSPICE simulation results verify a good agreement. Furthermore, our modeling technique can be implemented as a CAD tool for a primary estimation of the delay and the power consumption in complex circuits while retains an acceptable accuracy.

This paper presents a rapid and efficient modeling method, based on the microstrip lines theory, for the coupling between a device contact and the substrate backplane. We derive simple closed-form formulas to model spiral inductors as important substrate-noise sources in mixed-signal systems. The model has been verified via IE3D simulations up to 35 GHz, and is adaptable to CAD tools. We demonstrate that the accuracy of the proposed model is better than 8%.

This paper presents two rapid and yet accurate modeling methods for substrate coupling between a device contact and a substrate backplane. We discuss effects of physical parameters and geometrical characteristics of the contact and the substrate on the proposed models. We also derive model expressions for extraction of circuit-model elements of the substrate. Both methods are efficient for speed, memory usage, and adaptable to computer-aided design (CAD) tools for optimization tasks. The accuracy of both methods, the parametric modeling method and the microstrip line approximation method, is validated by comparing with the rigorous simulation data obtained from IE3D. Using the new models, we record a much higher speedup factor and extremely lower memory requirements compared to other published methods. The modeling methods are extended to two-layer structures and the models are applied to spiral inductors for verification purposes. In our research, we have validated the models over a wide range of frequencies up to 20 GHz.