3-D ICs can continue to improve power, performance, area, and cost beyond traditional Moore’s law scaling limitations by leveraging the third dimension and short vertical interconnects. Several recent studies present methodologies to implement 3-D ICs, but most of these studies implement each tier separately after partitioning a design into multiple tiers, resulting in inaccurate buffer insertion, which becomes more severe in advanced technology nodes. In this article, we present a new methodology called “Cascade2D flow” which utilizes design and microarchitecture insight for tier partitioning and implements 3-D ICs using 2-D commercial tools. By modeling vertical interconnects with sets of anchor cells and dummy wires, Cascade2D flow places, and routes and optimizes multiple tiers simultaneously in the 2-D version of a 3-D IC called “cascade2D design,” which enables accurate buffer insertion. Two flavors of 3-D ICs—monolithic 3-D (M3D) and face-to-face-bonded (F2F-bonded) 3-D ICs—of a commercial in-order, 32-bit application processor at foundry 28 nm, 14/16 nm, and predictive 7-nm technology nodes are implemented using this new methodology. We investigate the power, performance and area improvements of 3-D ICs over the 2-D counterparts to examine the efficacy of the methodology. Our new methodology outperforms the state-of-the-art 3-D IC design flows in the both flavors of 3-D ICs with up to$4\times $better power savings. In the best case, 3-D ICs from Cascade2D flow show 25% better performance at iso-power and 20% lower power at iso-performance.

As 2-D scaling reaches its limit, monolithic 3-D (M3D) IC is a leading contender for continuing equivalent scaling. Although M3D shows power and performance benefits over 2-D designs, designing a power delivery network (PDN) for M3D is challenging. In this paper, for the first time, we present a system-level PDN model of M3D designs focusing on both resistive (IR) and inductive (Ldi/dt) components of power supply integrity. In addition, we present frequency- and time-domain analyses of M3D PDNs. We show that the additional resistance in M3D PDNs, while being worse for resistive drops, improves resiliency against ac current noise showing 35.9% peak impedance reduction compared to 2-D PDNs during worst case resonant oscillations. Then, we present methodologies to improve power supply integrity of M3D designs based on the observations. Our optimization methodologies offer up to 32.6% and 17.0% static and dynamic voltage drop reduction compared to the baseline M3D designs, respectively, showing 9.0% lower dynamic voltage drop compared to the 2-D counterparts.

Standard cell libraries are the foundation for the entire back-end design and optimization flow in modern application-specific integrated circuit designs. At 7nm technology node and beyond, standard cell library design and optimization is becoming increasingly difficult due to extremely complex design constraints, as described in the ASAP7 process design kit (PDK). Notable complexities include discrete transistor sizing due to FinFETs, complicated design rules from lithography and restrictive layout space from modern standard cell architectures. The design methodology presented in this paper enables efficient and high-quality standard cell library design and optimization with the ASAP7 PDK. The key techniques include exhaustive transistor sizing for cell timing optimization, transistor placement with generalized Euler paths and back-end design prototyping for library-level explorations.

In the sub-7nm technology nodes, as the mask cost for printing the dense via layers increases dramatically with conventional lithography technique, industries are actively looking for some alternative techniques, such as E-beam, EUV or nanoimprint. In recent years, directed self-assembly (DSA) has been demonstrated to be a promising candidate to reduce the number of masks due to its pitch multiply ability by grouping several vias in the same DSA guiding patterns. A novel idea has been proposed recently to further reduce the mask cost by applying double block copolymer (double-BCP) materials for DSA lithography. However, it is also discovered that new challenges are introduced for the DSA pattern assignment and decomposition problem with double-BCP DSA. This paper discusses the design technology co-optimization (DTCO) for BCP materials and DSA-MP hybrid lithography. We show that it is necessary to consider the pitch-range of BCP materials for the DSA pattern assignment and decomposition. We first propose a pitch-range optimization method for the BCP material to minimize the potential DSA decomposition conflicts. We then solve the double-BCP pattern assignment and decomposition by formulating it to a maximum weighted independent set problem, and obtain the optimal solution with integer linear programming (ILP). We also propose a bounded approximation algorithm to solve the ILP problem more efficiently. The experimental results demonstrate that our pitch-range optimization method can quickly find the pitch-range that can minimize the decomposition conflicts. With the optimized pitch-ranges, double-BCP outperforms single-BCP by reducing more than 500 conflicts for very dense design. In addition, our proposed approximation algorithm solves the problem 38× faster than the ILP formulation.

As 2D scaling reaches its limit, monolithic 3D IC (M3D) is a leading contender to continue equivalent scaling. Although M3D shows power and performance benefits over 2D designs, designing a power delivery network (PDN) for M3D is challenging. In this paper, for the first time, we present a system-level PDN model of M3D designs focusing on both resistive (IR) and inductive (Ldi/dt) components of power-supply integrity. In addition, we present frequency- and time-domain analysis of the M3D PDN. We show that the additional resistance in the M3D PDN, while being worse for resistive drops, improves resiliency against current noise showing 35.9% peak impedance reduction during worst-case resonant oscillations.

Monolithic 3-D (M3D) IC is one of the potential technologies to break through the challenges of continued circuit power and performance scaling. In this paper, for the first time, we demonstrate the power benefits of M3D and present design guideline in a 7-nm FinFET technology node. The predictive 7-nm process design kit (PDK) and the standard cell library using both high-performance (HP) and low-standby-power (LSTP) device technologies are developed based on NanGate 45-nm PDK using accurate dimensional, material, and electrical parameters from publications and a commercial-grade tool flow. We implement full-chip M3D designs utilizing industry-standard physical design tools, and gauge the impact of M3D technology on performance, power, and area metrics. We also provide the design guidelines as well as a new partitioning methodology to improve M3D design quality. This paper shows that M3D designs outperform 2-D counterparts by 16% and 16.5% on average in terms of isoperformance total power reduction with 7-nm HP and LSTP cell library, respectively. This demonstrates the power benefits of M3D technology in both HP and low-power future generation devices.

Monolithic 3D IC (M3D) has the potential to provide a break-through in the power and performance scaling challenges. We, for the first time, present a comprehensive study of M3D on a commercial design across multiple technology nodes. The performance and power impact of M3D is investigated using a commercial, in-order, 32-bit application processor, implemented on foundry 28nm and 14/16nm process nodes, as well as a predictive 7nm node. We study the factors across the technology nodes that affect the efficiency of M3D, and propose a roadmap for optimum technology and design interaction that will enable the full entitlement of M3D.

Monolithic 3D IC (M3D) can continue to improve power, performance, area and cost beyond traditional Moore's law scaling limitations by leveraging the third-dimension and fine-grained monolithic inter-tier vias (MIVs). Several recent studies present methodologies to implement M3D designs, but most, if not all of these studies implement top and bottom tier separately after partitioning, which results in inaccurate buffer insertion. In this paper, we present a new methodology called ‘Cascade2D’ that utilizes design and micro-architecture insight to partition and implement an M3D design using 2D commercial tools. By modeling MIVs with sets of anchor cells and dummy wires, we implement and optimize both top and bottom tier simultaneously in a single 2D design. M3D designs of a commercial, in-order, 32-bit application processor at the foundry 28nm, 14/16nm and predictive 7nm technology nodes are implemented using this new methodology and we investigate the power, performance and area improvements over 2D designs. Our new methodology consistently outperforms the state-of-the-art M3D design flow with up to 4× better power savings. In the best case scenario, M3D designs from the Cascade2D flow show 25% better performance at iso-power and 20% lower power at isoperformance.

Monolithic 3D IC is an emerging technology to continuously satisfy demands for power reduction under challenges posed by traditional device scaling. In this paper, for the first time, we study power benefits of 4-tier monolithic 3D ICs compared with 2-tier monolithic 3D and 2D ICs. We present a tier partitioning methodology that significantly extends the capability of a state-of-the-art flow built for 2-tier monolithic 3D ICs. We develop two complete RTL-to-GDSII design flows to achieve this goal and offer quantitative comparisons. In addition, we study impacts of inter-tier via usage on 2-tier and 4-tier monolithic 3D ICs. Our experiments show that poorly controlled inter-tier via usage results in up to 6.05% degradation in total power savings. Thus, we develop an effective strategy to achieve inter-tier via configurations to optimize power metrics. Experiments show that 4-tier monolithic 3D ICs outperform 2-tier and 2D IC by 15% and 50% in terms of power and 25% and 75% in area under the same performance.

Monolithic 3D IC (M3D) is one potential technology to help with the challenges of continued circuit power and performance scaling. In this paper, for the first time, the power benefits of monolithic 3D IC (M3D) using a 7nm FinFET technology are investigated. The predictive 7nm Process Design Kit (PDK) and standard cell library for both high performance (HP) and low standby power (LSTP) device technologies are built based on NanGate 45nm PDK using accurate dimensional, material, and electrical parameters from publications and a commercial-grade tool flow. In addition, we implement full-chip M3D GDS layouts using both 7nm HP and LSTP cells and industry-standard physical design tools, and evaluate the resulting full-chip power, performance, and area metrics. Our study first shows that 7nm HP M3D designs outperform 7nm HP 2D designs by 16.8% in terms of iso-performance total power reduction. Moreover, 7nm LSTP M3D designs reduce the total power consumption by 14.3% compared to their 2D counterparts. This convincingly demonstrates the power benefits of M3D technologies in both high performance as well as low power future generation devices.

Self-aligned double patterning (SADP) is being considered for use at the 10-nm technology node and below for routing layers with pitches down to ~50 nm because it has better line edge roughness and overlay control compared to other multiple patterning candidates. To date, most of the SADP-related literature has focused on enabling SADP-legal routing in physical design tools while few attempts have been made to address the impact SADP routing has on local, standard cell (SC) I/O pin access. At the same time, via layers are used to connect the local SADP routing layers to the I/O pins on lower metal layers. Due to the high via density on the Via-1 layer, the litho-etch-litho-etch (LELE)-aware Via-1 design becomes a necessity to achieve legal pin access at the SC level. In this paper, we present the first study on SADP-aware pin access and layout optimization at the SC level. Accounting for SADP-specific and Via-1 design rules, we propose a coherent framework that uses depth first search, mixed integer linear programming, and backtracking method to enable LELE friendly Via-1 design and simultaneously optimize SADP-based local pin access and within-cell connections. Our experimental results show that, compared with the conventional approach, our framework effectively improves pin access of the SCs and maximizes the pin access flexibility for routing.

FinFETs have recently overtaken bulk CMOS transistors as the device of choice for systems-on-chip. This paper provides some background on FinFETs together with their associated manufacturing processes and shows how they influence physical design of standard cells as well as place & route and timing closure for larger blocks.

Self-Aligned Double Patterning (SADP) is being considered for use at the 10$nm$ technology node and below for routing layers with pitches down to ~50nm because it has better LER and overlay control compared to other multiple patterning candidates. To date, most of the SADP-related literature has focused on enabling SADP-legal routing in physical design tools while few attempts have been made to address the impact SADP routing has on local, standard cell (SC) I/O pin access. In this paper, we present the first study on SADP-aware pin access and layout optimization at the SC level. Accounting for SADP-specific design rules, we propose a coherent framework that uses Mixed Integer Linear Programming (MILP) and branch and bound method to simultaneously optimize SADP-based local pin access and within-cell connections. Our experimental results show that, compared with the conventional approach, our framework effectively improves pin access of the standard cells and maximizes the pin access flexibility for routing.

Looking forward along the technology roadmap, we see a complex, shifting landscape in which to attempt to ramp yield. Optical lithography is not providing any direct scaling benefit, and the available workarounds such as multiple patterning and mix-and-match lithography techniques greatly complicate design-technology co-optimization (DTCO) and yield/cost understanding. The silicon FinFET will give way to nanowires and/or new channel materials, and eventually force the examination of entirely new transistor topologies. Interconnect R's and C's will upset the FET/wire balance and with it some of our accumulated design/yield understanding, and reliability will play an increasing role in the determination of final cost. This talk will examine these technology roadmap topics with a view toward technology bring-up.

Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research. In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG). Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap.

The coming ten years promise great changes in silicon technology, with the end of planar bulk CMOS and the rise of interconnect parasitics to true significance. With such shifts in the underlying technology, the simple extrapolation of performance metrics may lead to pronounced prediction errors in design pathfinding. In this work, we utilize newly developed Predictive Technology Models for FinFETs aligned to the 2011 ITRS. Together with predictive interconnect models, we project performance and power landscape for the technology nodes from 20nm to 7nm. We present an overview of models, assess the advantage of FinFET over bulk CMOS devices, benchmark the scaling of critical design metrics, and illustrate major design barriers toward the 7nm node.

This paper discusses one of the key challenges of design-for-yield: namely, the difficulty in correlating observed behavior with modeled behavior. In order to achieve good parametric yield, the design process must account for a large number of sources of variability in the silicon, ranging from those inherent in the device and wire models themselves through approximations made in library modeling, extraction, tool algorithms and so on. The problem is further complicated by defects and systematic errors that can be present in early silicon but are expected to be fixed as part of the volume ramp. In addition, environmental factors such as temperature and power delivery must be understood, and variation in the measurement equipment must also be correctly accounted for. Examples are given for validating standard cell and memory based designs as well as a general methodology that can be used to enable chip bring-up.

Universal, semi-empirical MOSFET hole inversion layer mobility degradation models for use in circuit simulation programs such as SPICE are presented. By accurately predicting the mobility degradation due to acoustic phonon scattering and surface roughness scattering for p-channel MOSFETs at room temperature, these models eliminate the need for fitting parameters for each technology, which is required in the current SPICE level 3 model. The expressions reported accurately predict the mobility over a very wide range of channel doping concentrations, gate oxide thicknesses, gate voltage, and substrate bias, and they agree very well with recently published experimental mobility degradation data. When implemented in a circuit simulation code, these models will accurately determine the channel mobility in surface p-channel MOSFETs using only the channel doping concentration, gate oxide thickness, substate bias, and applied gate drive voltage as input parameters.>

Based on the physical insights provided by the universal mobility curve, an improved comprehensive universal model for effective electron mobility in inversion layers of n-channel MOSFETs is developed for circuit simulation. This model expresses the effective electron mobility at room temperature as a function of effective vertical field. It exhibits a high degree of accuracy for a wide range of different device characteristics, such as channel doping levels, gate oxide thicknesses, and channel dimensions. In addition, it predicts very well the effective mobility under the effects of substrate biases for gate voltages well above threshold, which is an improvement over earlier models. Moreover, this model has been developed with an emphasis on the functional dependence of mobility on high effective field, and is thus particularly accurate in that range of effective field. This is a significant advantage of the model since today's submicrometer MOSFETs typically operate at high effective fields.>

From the physical insights provided by the universal effective mobility versus effective vertical electric field curve for electrons in MOS inversion layers, a simple general expression for the gate voltage dependence of the effective electron mobility is derived for use in SPICE circuit simulation. This expression is quite accurate over a wide range of channel doping concentrations and gate oxide thicknesses, without the need for fitting parameters, such as the theta parameter of the current SPICE level 3 mobility degradation model. It is, therefore, a much more universal model than the present SPICE level 3 mobility expression. Furthermore, the relative accuracy of this new model compared to the current SPICE model is expected to increase at the higher vertical electric fields typical of submicrometer oxide semiconductor field effect transistors (MOSFETs).>