In this paper, a highly reliable multi-bit physically unclonable function (PUF) is proposed. The solution relies on an already tested two-transistor (2T) sub-threshold voltage divider as core circuit along with a multi-bit architecture able to carry out two highly stable bits from three bits generated by a proper entropy quantization. Twenty measured samples of the bitcell core were used to fit a customized Verilog-A model, which was then imported into Cadence Virtuoso environment for the architecture-level analysis. The proposed solution was tested across Monte Carlo simulations at both golden key (GK) and different environmental conditions, while also including the effect of noise. Simulation results prove the effectiveness in generating two highly stable bits for each cell after spatial majority voting and best stability selection. Indeed, no instability was observed in the 0-50 °C temperature range for the two output bits.

This paper explores a class of highly stable static monostable physically unclonable functions (PUFs) based on stacked sub-threshold voltage dividers between two nominally identical sub-circuits as bitcell core block. More specifically, compared to our previous works where two-transistor (2T) and four-transistor (4T) voltage divider based PUFs were presented and analyzed, here we propose two novel topological variants based on six-transistor (6T) and eight-transistor (8T) solutions which arise from adopting a proper reverse gate-biasing strategy within the stack with the aim of improving the resilience to on-chip noise and voltage variations, while keeping the area overhead low. These novel solutions, along with those already proposed, were tested in 180-nm CMOS technology. Raw measurements show a nominal (at 1.8 V and 25°C) bit error rate (BER) of 0.15% and 0.08% for the 6T- and 8T-based solutions, respectively, along with a BER variation of 0.016% and 0.002% per 0.1 V. With the implementation of a simple masking technique based on measurements at low supply voltage ($V_{DD} =0.3$V at 25 °C) along with a temporal majority voting (TMV) scheme, a BER of 0.006% and lower than$9.77\times 10^{-5}$%, which is the minimum observable BER for the adopted statistical set, was observed for the 6T-, and 8T-core based implementations, respectively, with a corresponding masking ratio of 8.71% and 7.59%. This is achieved with an area per bit of 5,$174F^{2}$(6T solution) and 6,$994F^{2}$(8T solution).

Smart tags are compact electronic devices affixed to or embedded into objects to facilitate identification, monitoring, and data exchange. Consequently, secure authentication of these tags is a crucial issue, as objects must reliably verify their identity before sharing sensitive information with other entities. The application of Physical Unclonable Functions (PUF) as a device's “digital fingerprint” has attracted significant attention, yet existing PUF-based authentication methods exhibit security vulnerabilities, either due to the authentication protocol itself or the limited reliability of the PUF technology used. Moreover, there has been a considerable focus on the software aspect, often overlooking the critical role of hardware design, which can become a target for attacks aimed at compromising the device's identity or act as a hindrance in the manufacturing process. In light of these points, this paper introduces an identification tag architecture that leverages PUF technology, focusing on authentication. This architecture features a straightforward but efficient authentication protocol, underpinned by a new and highly stable PUF model. The overall architecture encompasses particular hardware implementation aspects that significantly simplify the tag's enrollment phase and minimize vulnerabilities to attacks. The paper also describes a prototype of this identification tag and provide detailed insights into its application.

In this paper, a variation-aware simulation framework is introduced for hybrid circuits comprising MOS transistors and spintronic devices (e.g., magnetic tunnel junction-MTJ). The simulation framework is based on one-time characterization via micromagnetic multi-domain simulations, as opposed to most of existing frameworks based on single-domain analysis. As further distinctive capability, stochastic variations of the MTJ switching are explicitly incorporated through a Skew Normal distribution, which is adjusted to fit micromagnetic simulations. The framework is implemented in the form of Verilog-A look-up table based model, which assures easy integration with commercial circuit design tools, and very low computational effort. The framework is applied to non-volatile Flip-FIops as case study with 10,000 Monte Carlo runs.