In this paper, we address the problem of run-time resource management in non-ideal multiprocessor platforms where communication happens via the Network-on-chip (NoCs) approach. More precisely, we propose a system-level fault-tolerant technique for application mapping which aims at optimizing the entire system performance and communication energy consumption, while considering the occurrence of permanent, transient, and intermittent faults in the system. As the main theoretical contribution, we address the problem of spare core placement and its impact on system fault-tolerance (FT) properties. Then, we investigate several metrics and provide insight into the fault-aware resource management process for such non-ideal multiprocessor platforms. Experimental results show that our proposed resource management technique is efficient and highly scalable and significant throughput improvements can be achieved compared to the existing solutions that do not consider failures in the system.

In this paper, we argue that future systems need to be designed using a flexible user-centric design methodology geared primarily toward maximizing the user satisfaction (i.e., flow experience) rather than seeking mainly optimization of performance and power consumption. Compared to the traditional design, we aim at re-focusing the current design paradigm by placing the user behavior at the center of the design process and by using psychological variables such as user ability and motivation as the main drivers of this process. This allows systems to become more capable of promptly adapting to different users' needs and of enhancing short- and long-term user satisfaction. Preliminary results show the potential of this methodology for maximizing the users' positive experience when running embedded applications on multiprocessor platforms.

In this paper, we propose a run-time strategy for allocating application tasks to embedded multiprocessor systems-on-chip platforms where communication happens via the network-on-chip approach. As a novel contribution, we incorporate the user behavior information in the resource allocation process; this allows the system to better respond to real-time changes and to adapt dynamically to different user needs. Several algorithms are proposed for solving the task allocation problem while minimizing the communication energy consumption and network contention. When the user behavior is taken into consideration, we observe more than 70% communication energy savings (with negligible energy and run-time overhead) compared to an arbitrary contiguous task allocation strategy.

In this paper, we propose a user-centric design methodology targeting heterogeneous embedded systems-on-chip where communication happens via the network-on-chip approach. More precisely, in this new design methodology, we consider explicitly the information about the user experience and apply machine learning techniques to develop a design flow which aims at minimizing the workload variance; this allows the system to better adapt to different types of user needs and workload variations. Our experimental results show that by considering the user experience into the design space exploration step, the system platforms generated by our approach achieve more than 30% energy savings, on average, compared to the single platform derived from the traditional design flow; this implies that each system configuration we generate is highly suitable for the targeted class of user and workload behaviors.

In this paper, we present a design methodology for automatic platform generation of future heterogeneous systems where communication happens via the network-on-chip (NoC) approach. As a novel contribution, we consider explicitly the information about the user experience into a design flow which aims at minimizing the workload variance; this allows the system to better adapt to different types of user needs and workload variations. More specifically, we first collect various user traces from various applications and generate specific clusters using machine learning techniques. For each cluster of such user traces, depending on the architectural parameters extracted from high-level specifications, we propose an optimization method to generate the NoC system architecture. Finally, we validate the user-centric design space exploration using realistic traces and compare it to the traditional NoC design methodology.

In this paper, we propose a run-time strategy for allocating the application tasks to platform resources in homogeneous networks-on-chip (NoCs). As novel contribution, we incorporate the user behavior information in the resource allocation process; this allows system to better respond to real-time changes and adapt dynamically to user needs. Several algorithms are then proposed for solving the task allocation problem, while minimizing the communication energy consumption and network contention. If user behavior is taken into consideration, we observe about 60% communication energy savings (with negligible and energy runtime overhead) compared to an arbitrary task allocation strategy.

In this paper, we analyze the impact of network contention on the application mapping for tile-based network-on-chip (NoC) architectures. Our main theoretical contribution consists of an integer linear programming (ILP) formulation of the contention-aware application mapping problem which aims at minimizing the inter-tile network contention. To solve the scalability problem caused by ILP formulation, we propose a linear programming (LP) approach followed by an mapping heuristic. Taken together, they provide near-optimal solutions while reducing the runtime significantly. Experimental results show that, compared to other existing mapping approaches based on communication energy minimization, our contention-aware mapping technique achieves a significant decrease in packet latency (and implicitly, a throughput increase) with a negligible communication energy overhead.

Achieving effective run-time mapping on multiprocessor systems-on-chip (MPSoCs) is a challenging task, particularly since the arrival order of the target applications is not known a priori. This paper targets real-time applications which are dynamically mapped onto embedded MPSoCs, where communication happens via the Network-on-Chip (NoC) approach, and resources connected to the NoC have multiple voltage levels. We address precisely the energy- and performance-aware incremental mapping problem for NoCs with multiple voltage levels and propose an efficient technique (consisting of region selection and node allocation) to solve it. Moreover, the proposed technique allows for new applications to be added to the system with minimal in- terprocessor communication overhead. Experimental results show that the proposed technique is very fast, and as much as 50% communication energy savings can be achieved compared to using an arbitrary allocation scheme.

We propose a graph automorphism-based algorithm for computing maximal sets of symmetric inputs of circuits. It can be used to identify nonsymmetric inputs in a circuit and enhance the efficiency of input matching, library binding, as well as logic verification problems. We conduct the experiments on some benchmarks. The experimental results demonstrate that our approach distinguishes more non-symmetric inputs than that of previous work.