Custom architectures are often adopted as more efficient alternatives to general purpose processors in terms of performance and power. However, the design of such architectures requires experts both in hardware and the application domain. In this paper we propose a method for speeding up the design space exploration. Our method, based on Pareto points, identifies sets of solutions in terms of scalar units and vector units of certain length, fulfilling the throughput constraints for each application in a given set. Architectures can then be selected by combining these solutions, as starting points for a more thorough, model-based evaluation.

As custom architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modeling, while state-of-the-art constraint solvers enable optimal solutions for large problems, hinting a new method for code generation.

In this article, we present a constraint programming approach for solving hard design problems present when automatically designing specialized processor extensions. Specifically, we discuss our approach for automatic selection and synthesis of processor extensions as well as efficient application compilation for these newly generated extensions. The discussed approach is implemented in our integrated design framework, IFPEC , built using Constraint Programming (CP). In our framework, custom instructions, implemented as processor extensions, are defined as computational patterns and represented as graphs. This, along with the graph representation of an application, provides a way to use our CP framework equipped with subgraph isomorphism and connected component constraints for identification of processor extensions as well as their selection, application scheduling, binding, and routing. All design steps assume architectures composed of runtime reconfigurable cells, implementing selected extensions, tightly connected to a processor. An advantage of our approach is the possibility of combining different heterogeneous constraints to represent and solve all our design problems. Moreover, the flexibility and expressiveness of the CP framework makes it possible to solve simultaneously extension selection, application scheduling, and binding and improve the quality of the generated results. The article is largely illustrated with experimental results.

This paper presents a new method, based on constraint programming, for modeling and solving scheduling and instruction selection for processors extended with a functionally reconfigurable cell fabric. Our method models parallel reconfigurable architectures, the selection of application specific computational patterns and application scheduling. It takes also into account architectural constraints. The method provides efficient design space exploration that selects existing processor instructions and new instructions implementing computational patterns on a reconfigurable cell fabric. All instructions are scheduled enabling parallel instruction execution. Our method can be used directly for VLIW architectures by relaxing constraints concerning cell-processor data transfers. MediaBench and MiBench benchmarks have been used for evaluation and we obtained optimal results in many cases.

This paper presents a new constraint-driven method for computational pattern selection, mapping and application scheduling using reconfigurable processor extensions. The presented method is a part of DURASE system (Generic Environment for Design and Utilization of Reconfigurable Application-Specific Processors Extensions). The selected processor extensions are implemented as specialized processor instructions. They correspond to computational patterns identified as most frequently occurring or other interesting patterns in the application graph. Our methods can handle both time-constrained and resource-constrained scheduling. Experimental results obtained for the Media-Bench and Mi-Bench benchmarks show that the presented method ensures high speed-ups in application execution.

In this paper, we present a novel method for merging sets of computational patterns into a reconfigurable cell respecting design constraints and optimizing specific design aspects. Each cell can then be used in a run-time reconfigurable processor extension. Our method uses constraint programming to define the pattern merging problem and therefore can easily include design constraints and optimize different design aspects. Experiments carried out on Media-Bench test suite indicate 50% average reduction of cell area without increasing critical path.

This article presents a new tool for automatic design of application-specific reconfigurable processor extensions based on UPaK (Abstract U nified Pa tterns Based Synthesis K ernel for Hardware and Software Systems). We introduce a complete design flow that identifies new instructions, selects specific instructions and schedules a considered application on the newly created reconfigurable architecture. The identified extensions are implemented as specialized sequential or parallel instructions. These instructions are executed on a reconfigurable unit implementing all merged patterns. Our method uses specially developed algorithms for subgraph isomorphism that are implemented as graph matching constraints. These constraints together with separate algorithms are able to efficiently identify computational patterns and carry out application mapping and scheduling. Our methods can handle both time-constrained and resource-constrained scheduling. Experimental results show that the presented method provides high coverage of application graphs with small number of patterns and ensures high application execution speedup both for sequential and parallel application execution with reconfigurable processor extensions implementing selected patterns.

Program parallelization and distribution becomes increasingly important when new multi-core architectures and cheaper cluster technology provide ways to improve performance. Using declarative languages, such as constraint programming, can make the transition to parallelism easier for the programmer. In this paper, we address parallel and distributed search in constraint programming (CP) by proposing several load-balancing methods. We show how these methods improve the execution-time scalability of constraint programs. Scalability is the greatest challenge of parallelism and it is particularly an issue in constraint programming, where load-balancing is difficult. We address this problem by proposing CP-specific load-balancing methods and evaluating them on a cluster by using benchmark problems. Our experimental results show that the methods behave differently well depending on the type of problem and the type of search. This gives the programmer the opportunity to optimize the performance for a particular problem.

This paper presents a new method for automatic selection of application-specific processor extensions and shows how applications are scheduled on these new reconfigurable architectures. The extensions are implemented as specialized sequential or parallel instructions. They correspond to identified most frequently occurring computational patterns or other interesting patterns and are finally selected during mapping and scheduling. Our methods can handle both time-constrained and resource-constrained scheduling. Experimental results show that the presented method provides high coverage of application graphs with small number of patterns and ensures high application execution speed-up both for sequential and parallel application execution with processor extensions implementing selected patterns.

In this paper, we introduce a constraint programming-based approach for optimization of routing and reconfiguration overhead for a class of reconfigurable processor array architectures called weakly programmable. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for optimal routing of data between processors as well as for minimization of the routing area and the reconfiguration overhead when switching between the execution of these algorithms. In fact, applying the switching can be accomplished in just a few clock cycles. Our experiments confirm that our method can minimize routing overhead and reduce reconfiguration time significantly.

In this paper, we present a constraint programming-based approach for optimization of routing and reconfiguration overhead for a class of reconfigurable processor array architectures called weakly programmable. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for optimal routing of data between processor elements as well as for minimization of the routing area and the reconfiguration overhead when switching between the execution of these algorithms. Our experiments confirm that our method can minimize routing overhead and reduce reconfiguration time significantly.

In this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. Here, we support also multi-casting data transfers for the first time. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a few clock cycles. Moreover the communication network area can be minimized significantly (62% in average).

In this paper we discuss parallelization and distribution of problems modeled in a constraint programming (CP) framework. We focus on parallelization of depth-first search methods, since search is the most time-consuming task in CP. The current hardware development is moving towards multi-core processors and the cost of building distributed systems is shrinking. Hence, parallelization and distribution of constraint solvers is of increasing interest when trying to improve performance. One of the most important issues that arises in parallel computing is load-balancing, which requires a trade-off between processor load and communication. In this paper we present how reduced communication, at the cost of increased computation, can improve performance. Our experiments include global constraints, which are more powerful than binary constraints, but significantly more expensive to recompute in the average case. Our results show that recomputing data, rather than copying it, is sometimes faster even for problems that use global constraints. Given that copying is sometimes the better choice, we also present a method for combining copying and recomputation to create an even more powerful model of communication.

This paper presents a new method for computational patterns identification that forms basis for application specific instruction selection. The new algorithm is radically different from previous proposed methods. It is based on graph isomorphism constraint and constraint programming that makes it very flexible and provides opportunity to mix graph isomorphism constraints, other constraints and heuristic search for patterns in one formal environment. This algorithm takes into account graph structure and frequency of occurrence of patterns in application graphs. We have extensively evaluated our algorithm on MediaBench benchmarks. The experimental results indicate very good performance of our algorithm. It provides very high coverage for most graphs with a small number of identified computational patterns in a short amount of time.

In this paper we present a new method for high-level synthesis that enhances design flexibility, specialization and performance primarily conceived for programmable hardware. New programmable hardware devices often provide fast dedicated components that perform complex computations. Arbitrary complex computations can be efficiently extracted from the CDFG using our new graph matching constraint to produce final implementations that better suit the design to the targeted architecture. Our algorithm also reduces possible syntactic variances detecting semantically equivalent structures in the graph. This new graph matching constraint was integrated in our own Constraint Programming solver engine together with other constraints to naturally model the heterogeneous features present in the synthesis problem. The use of complex functional modules is taken into account in the optimization process during binding and scheduling yielding significantly shorter schedules and gains in terms of area and performance. We demonstrate our technique on a variety of HLS benchmarks and show that efficient design space exploration can be accomplished using this technique.

In this paper, we examine the impact of instruction level parallelism (ILP) on the full H.264 video encoding application and give quantitative performance measures of a superscalar architecture. Most research efforts have concentrated on the data intensive parts, such as kernels but these are taking less time from the entire execution as encoders are using new, more efficient algorithms. This important fact cannot be neglected since new video encoding standards have been proposed and the amount of other than data intensive computations has increased significantly. We observed significant improvement for the entire application when using superscalar architecture with out-of-order execution scheme. Tradeoffs in superscalar performance are also evaluated with combinations of measurements from simplescalar simulator

Java has proven to be a powerful language for software development. In this paper we show that it is also suitable for hardware compilation, making it an attractive language for embedded system development. Our compilation technique, which is presented here, is based on separating different aspects of the program and use dedicated and specialised optimisations and code generators for each aspect. In this paper we focus on efficient implementation of random memory accesses, i.e. reference intensive tasks, such as graph traversal. We show that for these tasks the hardware generated by our compiler is up to 1.8 times faster than a software implementation. We also show how recursive algorithms can be mapped to hardware using our tool.

This paper presents a novel method to generate optimized architecture of hardware processes implemented on "system on a programmable chip" (SoPC). The hardware processes are the applications tailored "cells" in the processor-coupled polymorphous fabric (Ch. Wolinski et al., 2003, Ch. Wolinski et al., 2002) implemented on the reconfigurable SoPC platform. In order to obtain optimized high performance pipelined architecture each process implementing repetitive conditional behavior with possible inter-iteration dependencies is scheduled under hardware resource constraints using "fabric cell synthesis tool" (FAST). The scheduling problem is defined and solved using constraints programming approach. This approach makes it possible to obtain optimal solutions in terms of execution time and number of registers for a number of real cases. Our method is illustrated using a simple example and a part of the "CORDIC" application (S.F. Hsiao et al., 1991). The final design is implemented on a reconfigurable platform that shows feasibility of our approach. Optimal schedules are achieved for both discussed applications.

This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. The input to our algorithm is an application given as an annotated task graph and a specification of a multi-layer memory architecture. The algorithm produces Pareto trade-off points representing different multi-objective execution options for the whole application. Different metrics are used to estimate parameters for application-level Pareto points obtained by merging all Pareto diagrams of the tasks composing the application. We estimate application execution time although the final scheduling is not yet known. The algorithm makes it possible to trade off the quality of the results and its runtime depending on the used metrics and the number of levels in the hierarchical composition of the tasks' Pareto points. We have evaluated our algorithm on a medical image processing application and randomly generated task graphs. We have shown that our algorithm can explore huge design space and obtain (near) optimal results in terms of Pareto diagram quality.

This paper presents our studies on the effects of using SIMD processor extension developed to enhance the processor performance for streaming applications. Our approach was evaluated using MPEG-4 encoding application as benchmark. Although MPEG-4 consists of many different operations, we concentrated on the sum of absolute differences (SAD), a major part of the motion estimation. The SAD was chosen because it is one of the most frequently used operations in MPEG-4 encoding. It is estimated to consume between 40%-80% of the total video encoding time when implemented on a general purpose processor. We have performed an extensive evaluation of our architecture extension. This evaluation showed that it is possible to achieve high performance with acceptable power consumption. We obtained about two times performance improvement for MPEG-4 encoding with roughly the same power consumption.

This paper presents a method to obtain an optimized static schedule of CSP-like communications between a collection of concurrent hardware processes implemented on "system on a programmable chip" (SoPC). The hardware processes are the applications tailored "cells" in the processor-coupled polymorphous fabric (Wolinski et al., 2003 and Wolinski et al., 2002) implemented on the Altera Excalibur Arm SoPC platform. In our global approach, a static communications schedule is adopted to reduce hardware overhead due to inter-cells message transfer synchronization and to speed-up application execution. The scheduling problem is defined and solved using constraints programming approach. This approach makes it possible to obtain optimal communication schedules in a number of real cases. It makes also possible to easily generate pipelined schedules that improve significantly performance of the final implementation. Our method is illustrated with a fabric-based implementation of the K-means clustering algorithm. An optimal communication scheduled is achieved for this application.

This paper presents a novel approach to scheduling communications among concurrent hardware processes mapped onto a "System on a Programmable Chip." Point-to-point, broadcast and multi-cast ommunication types are supported. The algorithm has been prototyped on the Processor-Coupled Polymorphous Fabric for the Altera Excalibur Arm architecture. The communication schedule problem has been specified using Constraints Programming. The advantages of our method are the following: Application of a general constraint solver makes it possible to express many different sorts of constraints in a uniform manner. All imposed constraints are handled by the solver concurrently which increases the chances of obtaining optimal results. The scheduler guarantees that loops periods are the same for each iteration so the smaller controllers can be generated. The method has been illustrated with a Fabric-based implementation of the K-means clustering algorithm for which an optimal communication schedule has been achieved.

This paper presents a novel partial assignment technique (PAT) that decides which tasks should be assigned to the same resource without explicitly defining assignment of these tasks to a particular resource. Our method simplifies the assignment and scheduling steps while imposing a small or no penalty on the final solution quality. This technique is specially suited for problems which have different resources constraints. Our method does not cluster tasks into a new task, as typical clustering techniques do, but specifies which tasks need to be executed on the same processor.Our experiments have shown that PAT, which may produce non linear groups of tasks, gives better results than linear clustering when multi-resource constraints are present. Linear clustering was proved to be optimal comparing to all other clusterings for problems with timing constraints only. In this paper, we show that, if used for multi-resource synthesis problem, as it is often used nowadays, linear clustering will produce inferior solutions.

Energy consumption reduction is today an important design issue for all kinds of digital systems. Offering both flexibility and efficient energy management, variable speed processor architectures are prefered for low energy consumption even in hard real-time systems. For this type of systems, the main approach consists in trading speed for lower energy while meeting all deadlines. For tasks with varying execution time, speed scheduling is most efficient if performed at run-time. This paper presents a new ordering technique for such tasks, that reduces the energy consumption resulting from the run-time speed scheduling. Without affecting the real-time behavior, our Uncertainty-Based Scheduling (UBS) is a low complexity but energy-efficient method that can be applied on top of already existent real-time scheduling techniques, such as EDF. These claims are backed up by extensive simulation results accompanied by measurements on a platform based on an Intel 180200 XScale processor.

This paper describes a new method for modeling and solving different scheduling and resource assignment problems that are common in high-level synthesis (HLS) and system-level synthesis. It addresses assignment of resources for operations and tasks as well as their static, off-line scheduling. Different heterogeneous constraints are considered for these problems. These constraints can be grouped into two classes: problem-specific constraints and design-oriented constraints. They are uniformly modeled, in our approach, by finite domain (FD) constraints and solved using related constrained programming (CP) techniques. This provides a way to improve quality of final solutions. We have developed in Java a constraint solver engine, JaCoP ( Ja va Co nstraint P rogramming), to evaluate this approach. This solver and a related framework make it possible to model different resource assignment and scheduling problems, and handle them uniformly. The JaCoP prototype system has been extensively evaluated on a number of HLS and system-level synthesis benchmarks. We have been able to obtain optimal results together with related proofs of optimality for all HLS scheduling benchmarks and for all explored design styles (except one functional pipeline design). Many system-level benchmarks can also be solved optimally. For large randomly generated task graphs, we have used heuristic search methods and obtained results that are 1--3% worse than lower bounds or optimal results. These experiments have proved the feasibility of the presented approach.

Recently substantial research has been devoted to Unmanned Aerial Vehicles (UAVs). One of a UAV's most demanding subsystem is vision. The vision subsystem must dynamically combine different algorithms as the UAVs goal and surrounding change. To fully utilize the available hardware, a run time system must be able to vary the quality and the size of regions the algorithms are applied to, as the number of image processing tasks changes. To allow this the run time system and the underlying computational model must be integrated. In this paper we present a computational model suitable for integration with a run time system. The computational model is called Image Processing Data Flow Graph (IP-DFG). IP-DFG has been developed for modeling of complex image processing algorithms. IP-DFG is based on data flow graphs, but has been extended with hierarchy and new rules for token consumption, which makes the computational model more flexible and more suitable for human interaction. In this paper we also show that IP-DFGs are suitable for modelling expressions, including data dependent decisions and iterations, which are common in complex image processing algorithms.

The work presented in this paper addresses minimization of the energy consumption of a system during system-level design. The paper focuses on scheduling techniques for architectures containing variable supply voltage processors, running dependent tasks. We introduce our new approach for Low-Energy Scheduling (LEneS) and compare it to two other scheduling methods. LEneS is based on a list-scheduling heuristic with dynamic recalculation of priorities, and assumes a given allocation and assignment of tasks to processors. Our approach minimizes the energy by choosing the best combination of supply voltages for each task running on its processor. The set of experiments we present shows that, using the LEneS approach, we can achieve up to 28% energy savings for the tightest deadlines, and up to 77% energy savings when these deadlines are relaxed by 50%.

This paper presents a new high-level synthesis (HLS) approach which addresses the problem of synthesis of conditional behaviors. In proposed methodology, the conditional behaviors are represented by Hierarchical Conditional Dependence Graphs (HCDG) and synthesized using derived Constraints Logic Programming (CLP) models. Our synthesis methods exploit multicycle operations and chaining as well as conditional resource sharing and speculative execution at the same time. These techniques are essential in HLS and the experiments carried out using the developed prototype system showed good performance of the synthesized designs and proved the feasibility of the presented approach.

This paper presents an approach to modeling of task graphs using finite domain constraints. The synthesis of such models into an architecture consisting of microprocessors, ASICs and communication devices, is then defined as an optimization problem and it is solved using constraint solving techniques. The presented approach offers an elegant and powerful modeling technique for different architecture features as well as heterogeneous constraints. The extensive experimental results prove the feasibility of this approach.

We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared buses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

This paper presents an RT level partitioning approach for sequential circuits described as data path and control part. The data path of a circuit is partitioned at some hard-to-test points detected by an RT level testability analysis algorithm. These points are then made directly accessible by DFT techniques. The control part is also modified to control the circuit in normal mode and test mode. In the normal mode, the circuit is controlled to perform its function, while in the test mode, all partitions are controlled independently. As a result, test quality is improved by independent test generation and test application for every partition. The partitioning complexity is reduced by the use of testability analysis results and the area overhead is lower than that of full scan designs for most benchmarks we used. Experiments show results of the approach as compared with no scan, partial scan and full scan schemes.

This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer level. The algorithms are used to specify the behaviors of the hardware to be designed. They are first translated into a formal representation model which is based on timed Petri nets and consists of separate but related descriptions of control and data path. The formal model is used as an intermediate design representation and supports an iterative transformation approach to high-level synthesis. The basic idea is that once the behavioral specification is translated into the initial design representation, it can be viewed as a primitive implementation. Correctness-preserving transformations are then used to successively transform the initial design into an efficient implementation. Selection of transformations is guided by an optimization strategy which makes design decisions concerning operation scheduling, data path allocation, and control allocation simultaneously. The integration of these several synthesis subtasks has resulted in a better chance to reach the globally optimal solution. Experimental results show that our approach produces improved register-transfer designs, especially in the cases when the designed hardware consists of data paths and control logics that are tightly coupled.>