Cyber-environments have become increasingly popular in disseminating scientific and educational resources. One of the primary methodologies for evaluating the scholarly impact of cyber-environment is through bibliometric and scientometrics analyses of publication and citation data. However, it is often difficult to create a workflow and software environment that can address this problem in serious ways. This article presents the software architecture for creating a web-based interface for managing citations and demonstrating visually the scholarly impact of a cyber-environment - nanoHUB.org, which has served over 310,000 users worldwide in just the last 12 months.

CMOS scaling enabled simultaneous system throughput scaling by concurrent delay, power, and area shrinks with thanks to Moore's law. System scaling is getting more difficult with the limitations in interconnect and bandwidth per power as well as the difficulties and cost of monolithic integration. This requires a holistic approach for an optimal balance of performance and power under the limits of technology. This paper covers a portfolio of More Moore technologies for power-aware device enabling value proposition for system scaling - where requirements and gaps will be addressed in the ITRS2.0 roadmap.

The science gateway nanoHUB.org is the world's largest nanotechnology user facility, serving 167, 196 users in 2010 with over 2,300 resources including 189 simulation programs. Surveys of nanoHUB users and automated usage analysis find widespread simulation use in formal classroom education, thereby connecting recent research more rapidly and closely to education. Analysis of 719 citations in the scientific literature by over 1,300 authors to nanoHUB.org resources documents use of simulation programs by new research collaborations, by researchers outside of the community originating the program, and by experimentalists. The publication and author networks reveal research collaborations and capacity building through knowledge transfer. Analysis of secondary citations documents the quality of the conducted research with an h-index of 30 after just 10 years of operation. Our analysis proves with quantitative metrics that impactful research can be conducted by an ever growing research community. We argue that HUBzeroTM technology and the user-focused design and operation of nanoHUB.org are keys to success that can be transferred to other science gateways.

In the last few years, evolutionary computing (EC) approaches have been successfully used for many real world optimization applications in scientific and engineering areas. One of these areas is computational nanoscience. Semi-empirical models with physics-based symmetries and properties can be developed by using EC to reproduce theoretically the experimental data. One of these semi-empirical models is the Valence Force Field (VFF) method for lattice properties. An accurate understanding of lattice properties provides a stepping stone for the investigation of thermal phenomena and has large impact in thermoelectricity and nano-scale electronic device design. The VFF method allows for the calculation of static properties like the elastic constants as well as dynamic properties like the sound velocity and the phonon dispersion. In this paper a parallel genetic algorithm (PGA) is employed to develop the optimal VFF model parameters for gallium arsenide (GaAs). This methodology can also be used for other semiconductors. The achieved results agree qualitatively and quantitatively with the experimental data.

We present a multi-dimensional, atomistic, quantum transport simulation approach to investigate the performances of realistic nanoscale transistors for various geometries and material systems. The central computation consists in solving the Schrödinger equation with open boundary conditions several thousand times. To do that, a Wave Function approach is used since it can be relatively easily parallelized. To further improve the computational efficiency, three additional levels of parallelization are identified, the work load is optimally balanced between the CPUs, computational interleaving is applied where possible, and a mixed precision scheme is introduced. Using two different device types, a high electron mobility and a band-to-band tunneling transistor, sustained performances up to 1.28 PFlop/s in double precision (55% of the peak performance) and 1.44 PFlop/s in mixed precision are reached on 221,400 cores on the CRAY-XT5 Jaguar at Oak Ridge National Lab.

Physics-based simulation of electron transport in nanoelectronic devices requires the solution of thousands of highly complex equations to obtain the output characteristics of one single input voltage. The only way to obtain a complete set of bias points within a reasonable amount of time is the recourse to supercomputers offering several hundreds to thousands of cores. To profit from the rapidly increasing availability of such machines we have developed a state-of-the-art quantum mechanical transport simulator dedicated to nanodevices and working with four levels of parallelism. Using these four levels we demonstrate that an almost ideal scaling of the walltime up to 32768 processors with a parallel efficiency of 86% is reached in the simulation of realistically extended and gated field-effect transistors. Obtaining the current characteristics of these devices is reduced to some hundreds of seconds instead of days on a small cluster or months on a single CPU.

The Network for Computational Nanotechnology (NCN) has developed a science gateway at nanoHUB.org for nanotechnology education and research. Remote users can browse through online seminars and courses, and launch sophisticated nanotechnology simulation tools, all within their web browser. Simulations are supported by a middleware that can route complex jobs to grid supercomputing resources. But what is truly unique about the middleware is the way that it uses hardware accelerated graphics to support both problem setup and result visualization. This paper describes the design and integration of a remote visualization framework into the nanoHUB for interactive visual analytics of nanotechnology simulations. Our services flexibly handle a variety of nanoscience simulations, render them utilizing graphics hardware acceleration in a scalable manner, and deliver them seamlessly through the middleware to the user. Rendering is done only on-demand, as needed, so each graphics hardware unit can simultaneously support many user sessions. Additionally, a novel node distribution scheme further improves our system's scalability. Our approach is not only efficient but also cost-effective. Only a half-dozen render nodes are anticipated to support hundreds of active tool sessions on the nanoHUB. Moreover, this architecture and visual analytics environment provides capabilities that can serve many areas of scientific simulation and analysis beyond nanotechnology with its ability to interactively analyze and visualize multivariate scalar and vector fields.

In this work we present a hardware-accelerated direct volume rendering system for visualizing multivariate wave functions in semiconducting quantum dot (QD) simulations. The simulation data contains the probability density values of multiple electron orbitals for up to tens of millions of atoms, computed by the NEMO3-D quantum device simulator software run on large-scale cluster architectures. These atoms form two interpenetrating crystalline face centered cubic lattices (FCC), where each FCC cell comprises the eight corners of a cubic cell and six additional face centers. We have developed compact representation techniques for the FCC lattice within PC graphics hardware texture memory, hardware-accelerated linear and cubic reconstruction schemes, and new multi-field rendering techniques utilizing logarithmic scale transfer functions. Our system also enables the user to drill down through the simulation data and execute statistical queries using general-purpose computing on the GPU (GPGPU).

The paper addresses the use of evolutionary algorithms in the design of electronic devices and circuits. In particular, the paper introduces the idea of evolutionary design of nanodevices, and illustrates it with the design of a resonant tunneling diode. A second experiment, this time using CMOS microdevices, illustrates the use of evolutionary algorithms for circuit design. The experiments were facilitated by an evolutionary design tool developed around a parallel implementation of genetic algorithms (using PGAPack), and device/circuit simulators (NEMO and SPICE). It is speculated that in the future, devices and circuits may be simultaneously co-designed.