Supervised transfer learning has received considerable attention due to its potential to boost the predictive power of machine learning in scenarios where data are scarce. Generally, a given set of source models and a dataset from a target domain are used to adapt the pre-trained models to a target domain by statistically learning domain shift and domain-specific factors. While such procedurally and intuitively plausible methods have achieved great success in a wide range of real-world applications, the lack of a theoretical basis hinders further methodological development. This paper presents a general class of transfer learning regression called affine model transfer, following the principle of expected-square loss minimization. It is shown that the affine model transfer broadly encompasses various existing methods, including the most common procedure based on neural feature extractors. Furthermore, the current paper clarifies theoretical properties of the affine model transfer such as generalization error and excess risk. Through several case studies, we demonstrate the practical benefits of modeling and estimating inter-domain commonality and domain-specific factors separately with the affine-type transfer models.

This article presents an area- and power-efficient transmission/receiving (TX/RX)-isolation switch implemented in a 3072-ch ultrasound (US) in-probe 2-D array transceiver application-specific integrated circuit (ASIC) for real-time 3-D imaging. Conventional T/R switches that protect low voltage (LV) receivers from high voltage (HV) bipolar pulses require at least four HV-MOSFETs. The proposed dynamic gate–source shunt topology, which utilizes a negative-HV-transmit-driven shunt switch, eliminates area- and power-hungry HV-level shifters and ensures the OFF state of our T/R switch for HV/LV isolation during TX periods. In addition, source-driven HV-PMOS for ON/OFF control enables both gate charging and discharging using a single HV-PMOS. Thus, our T/R switch enables implementation with only three HV-MOSFETs for the first time in the world. The HV-level-shifter-less architecture also enables static-power-free operation in TX periods and consumption of only$12.1~\mu \text{W}$in RX periods. Further, sequential input impedance control suppresses switching noise, which causes unwanted sound transmitted during TX to RX switching, by −18.1 dB. Moreover, by preparing an attenuation mode, a per-channel TX to RX self-loopback test can be performed. This function provides an on-wafer ac test without probing 3072 electrodes and it can be applied to the field diagnosis of assembled US probes.

A method for improving a visualized preference transition network by screening nodes in the network, where a node represents a product item, is described. The original preference transition network was developed not only for visualizing customer movements/trends in selecting items but also for finding the features of items. However, understanding such movements/trends and features is difficult when the network has many nodes and links. To solve this problem, the proposed method is a sensitivity analysis for identifying redundant nodes and links with adjustment of the threshold expressed by the Simpson coefficient. The effectiveness of this method was shown through a numerical experiment for 172 kinds of products, 2,227 customers, and their 90,000 sales records.

This paper proposes a hotel recommender system based on sales records. Basic premise under the research is that the sales records include the user's preference relations among hotels. The proposed system recommends hotels based on preference transition network when a user selects a hotel. This paper describes four steps procedure for building the preference transition network proposes in detail. The proposed recommender system is available for repeatable purchase without explicit product evaluation. The features of the prototype system are also illustrated.

As the interconnection delays control the LSI performance, the LSI performance estimation at higher design level becomes more difficult. In this paper a new LSI performance model for the estimation is described, which is made up by adopting a new clock-skew model to the SUSPENS (Stanford University System Performance Simulator) model. Using the model, it is cleared that a specific block size, where the line delay overcomes the block cycle time, becomes shorter as the LSI generation proceeds.

Discusses the problem of locating logic design errors, and proposes an algorithm to solve it. Based on the results of logic verification, the authors introduce an input pattern for locating design errors. The pattern contains only one Boolean variable X/X and is used to sensitize the design errors. An algorithm for locating single design errors with the input patterns has been developed. Experimental results have shown the effectiveness of the input patterns and the algorithm for locating single design errors.>

A multiprocessor which carries out multiple image recognition in parallel is proposed. It has been applied to an automatic routing algorithm for electronic CAD. The algorithm handles thousands of image planes. Each plane corresponds to the routing area of each net. Design rule check and path search are performed using image processing techniques for those planes. The multiprocessor architecture was evaluated by a software simulator and was found to achieve higher throughput, especially in the case of using a large number of processors.>

This paper describes the FS-4OOM submarine system which has a total system capacity of 17 280 two-way voice channels. It gives the major system parameters and system design. In addition, it discusses transmission characteristics of the system including the results of a longterm stability test carried out from January 1982 to February 1984 in Sagami Bay, in the Yahatano Sea area off the coast of the Izu Peninsula.