The ability to plan ahead efficiently is key for both living organisms and artificial systems. Model-based planning and prospection are widely studied in cognitive neuroscience and artificial intelligence (AI), but from different perspectives—and with different desiderata in mind (biological realism versus scalability) that are difficult to reconcile. Here, we introduce a novel method to plan in POMDPs— Active Inference Tree Search (AcT)—that combines the normative character and biological realism of a leading planning theory in neuroscience (Active Inference) and the scalability of tree search methods in AI. This unification enhances both approaches. On the one hand, tree searches enable the biologically grounded, first principle method of active inference to be applied to large-scale problems. On the other hand, active inference provides a principled solution to the exploration–exploitation dilemma, which is often addressed heuristically in tree search methods. Our simulations show that AcT successfully navigates binary trees that are challenging for sampling-based methods, problems that require adaptive exploration, and the large POMDP problem ‘ RockSample’ —in which AcT reproduces state-of-the-art POMDP solutions. Furthermore, we illustrate how AcT can simulate neurophysiological responses (e.g., in the hippocampus and prefrontal cortex) of humans and other animals that solve large planning problems. These numerical analyses show that Active Tree Search is a principled realisation of neuroscientific and AI planning theories, offering biological realism and scalability.

Active Inference is a computational framework used in neuroscience and cognitive science that characterises perception, planning and action in terms of probabilistic inference and the minimisation of variational free energy. cpp-AIF is a header-only C++ library that provides a powerful and flexible tool for implementing Active Inference for Partially Observable Markov Decision Processes through multi-core computing. Compared with existing software, cpp-AIF is cross-platform and improves performance, memory management, and usability.

This paper describes the architecture and hardware implementation of an embedded, low-cost and low-power dense stereo reconstruction system, running at 30 fps at VGA resolution. The processing pipeline includes an initial image rectification stage, a cost generation unit based on the non-parametric census transform, a state-of-the-art Semi-Global cost optimization stage, and a final minimization and noise suppression step. The hardware implementation is based on a Xilinx ZynqTMSystem-on-Chip, which besides the FPGA provides a physical dual-core ARM CPU, which is exploited for control and to deliver output over the integrated Gigabit Ethernet connection.

SUMMARY: Elucidation of molecular targets of a compound [mode of action (MoA)] and its off-targets is a crucial step in drug development. We developed an online collaborative resource (MANTRA 2.0) that supports this process by exploiting similarities between drug-induced transcriptional profiles. Drugs are organized in a network of nodes (drugs) and edges (similarities) highlighting 'communities' of drugs sharing a similar MoA. A user can upload gene expression profiles before and after drug treatment in one or multiple cell types. An automated processing pipeline transforms the gene expression profiles into a unique drug 'node' embedded in the drug-network. Visual inspection of the neighbouring drugs and communities helps in revealing its MoA and to suggest new applications of known drugs (drug repurposing). MANTRA 2.0 allows storing and sharing user-generated network nodes, thus making MANTRA 2.0 a collaborative ever-growing resource. AVAILABILITY AND IMPLEMENTATION: The web tool is freely available for academic use at http://mantra.tigem.it.

Regulation of gene expression is a carefully regulated phenomenon in the cell. “Reverse-engineering” algorithms try to reconstruct the regulatory interactions among genes from genome-scale measurements of gene expression profiles (microarrays). Mammalian cells express tens of thousands of genes; hence, hundreds of gene expression profiles are necessary in order to have acceptable statistical evidence of interactions between genes. As the number of profiles to be analyzed increases, so do computational costs and memory requirements. In this work, we designed and developed a parallel computing algorithm to reverse-engineer genome-scale gene regulatory networks from thousands of gene expression profiles. The algorithm is based on computing pairwise Mutual Information between each gene-pair. We successfully tested it to reverse engineer the Mus Musculus (mouse) gene regulatory network in liver from gene expression profiles collected from a public repository. A parallel hierarchical clustering algorithm was implemented to discover “communities” within the gene network. Network communities are enriched for genes involved in the same biological functions. The inferred network was used to identify two mitochondrial proteins.

Abstract The Block Conjugate Gradient algorithm (Block‐CG) was developed to solve sparse linear systems of equations that have multiple right‐hand sides. We have adapted it for use in heterogeneous, geographically distributed, parallel architectures. Once the main operations of the Block‐CG (Tasks) have been collected into smaller groups (subjobs), each subjob is matched by the middleware MJMS (MPI Jobs Management System) with a suitable resource selected among those which are available. Moreover, within each subjob, concurrency is introduced at two different levels and with two different granularities: the coarse‐grained parallelism to perform independent tasks and the fine‐grained parallelism within the execution of a task. We refer to this algorithm as to multi‐grained distributed implementation of the parallel Block‐CG. We compare the performance of a parallel implementation with the one of the distributed implementation running on a variety of Grid computing environments. The middleware MJMS—developed by some of the authors and built on top of Globus Toolkit and Condor‐G—was used for co‐allocation, synchronization, scheduling and resource selection. Copyright © 2010 John Wiley & Sons, Ltd.

Application domains of wireless sensor networks are emerging day-by-day, so developers are creating software components at various layers by using platforms such as MANTIS, TinyOS or ZigBee. Since these platforms are quite different in terms of programming paradigm and provided APIs, porting applications between them is difficult and expensive. In this paper, we show techniques that might be used to dramatically ease the porting application code between different software platforms for WSNs.

Showing functional correctness by simulation before implementation, and preserving it by automated code generation, is extremely useful to reduce the development time for an embedded application. This is even more true for wireless sensor networks, since their nodes often provide very rudimentary debugging facilities, and sufficiently large networks for realistic analysis may be expensive to deploy. While this approach, also known as model-based design, is becoming quite standard for several domains that have similar constraints as wireless sensor networks, such as automotive electronics, there is a lack of tools for this purpose in the WSN world. In order to fill this gap, in this paper we present a framework (based on Simulink, Stateflow and Embedded Coder) in which an engineer can create sensor network components (both at the application and at the protocol level) that can be used as building blocks to model, simulate and automatically generate code for different underlying platforms and operating systems.

Modern embedded systems must execute a variety of high performance real-time tasks, such as audio and image compression, channel coding and encoding, etc. Reconfigurable platforms can effectively be used in these cases, because they allow to re-use the architecture for as many applications as possible. The paper describes the implementation of a UMTS turbo-decoder on one such platform, the XiRisc reconfigurable processor. Our goal is to test the development framework and design flow that we already developed on a real industrial example. Our results shows that, with some manual effort from the designer, very good performance improvements can be achieved, using a flow close to embedded software development.

The paper describes the architecture of an image coprocessor based on a linear array of elementary processors. The system has been designed for real-time vision applications and embeds a direct I/O interface to a camera device. The instruction set of the elementary processors is based on morphological match operators on a reduced 5/spl times/5 neighborhood. Two additional communication mechanisms, one fixed and one programmable, provide both global and multiple communication channels among processing elements which are not directly connected.>

The PAPRICA project started in 1988 as an experimental VLSI architecture devoted to the efficient computation of data with two-dimensional structure. The main goal of the project is to develop a subsystem that could operate as an attached processing unit to a standard workstation and in perspective as a specialized processing module in dedicated systems devoted to low level image analysis, cellular neural networks emulation, DRC algorithms. The architecture has been extensively used for basic low level image analysis tasks up to optical flow computation and feature tracking, showing encouraging performance even in the first prototype version. The authors discuss the actual implementation and present a critical analysis of the project, allowing to identify some crucial points of PAPRICA design (and of array processors in general) that must be carefully considered in the case of redesign.>

Stochastic models of contention for shared resources in an experimental multiprocessor prototype are presented and are validated with simulation and measurement results. Three modeling techniques are used (stochastic Petri nets, Markov chains, and queueing networks) that represent the system operations as Markovian stochastic processes. Each technique is best suited to a specific stage of the analysis. An integrated use of these techniques represents a very powerful tool for the performance analysis of multiprocessor systems and provides ways of investigating several extensions of the prototype architecture. Simulation results and measurements performed on the hardware prototype validate the analysis and show that the accuracy of the analytical results is excellent.