Custom layouts of digital blocks are often used in mixed-signal designs in order to meet the critical performance requirements. Unlike traditional standard-cell based digital placement, custom-cell based digital placement may need additional manual help and intervention to achieve higher performance. The need for manual intervention is primarily due to the inability of modern analytical placers in delivering satisfactory performance on placing designs without pre-placed blocks. While most design flow works in a flat or top-down fashion, custom digital design generally works in a bottom-up fashion that there is no prior knowledge on I/O pin plan since it is changeable by the owners of modules. Without any or very few fixed I/O locations, modern analytical placers tend to produce unsatisfactory results. In this work, we propose a method, mimicking the process of making beds, to guide state-of-the-art analytical placers to deliver better placement results. With the crafted pseudo anchors and nets, total HPWL on Capo10.5 [1], mPL6 [2], NTUplace3 [3] and VDAPlace [4] have improved by 2.92%, 8.69%, 25.26% and 10.72% respectively on a set of industry custom digital designs and improved by 2.19%, 4.34%, 36.09%, and 14.27% respectively on Peko-Suite1 benchmarks.

Improving routability during both global and detailed routing stage has become a critical problem in modern VLSI design. In this work, we propose a placement framework that offers a complete coverage solution in considering both global and detailed routing congestion. A placement migration strategy is proposed, which improves detailed routing congestion while preserving the placement integrity that is optimized for global routability. Using the benchmarks released from ISPD2014 Contest, practical design rules in advanced node design are considered in our placement framework. Evaluation on routability of our placement framework is conducted using commercial router provided by the 2014 ISPD Contest organizers. Experimental results show that the proposed methodologies can effectively improve placement solutions for both global and detailed router.

The issue on reliability of the device becomes more critical as power density of device progressively increases with advancement of technology nodes. Smaller transistor and hence thinner gate oxide implies transistors are more vulnerable against an Electrostatic Discharge (ESD) event. Among the test models in ESD, Charged Device Model (CDM) has greater potential to cause catastrophic damage to the device due to its faster and larger discharging current. To protect against a CDM event, power clamps are placed across the design to offer a low resistance discharge path. However, conventional power clamp placement method to place power clamps generally relies on design experience. In this work, we propose a power clamp placement algorithm that places power clamp at strategic location which can effectively minimize number of power clamps while achieving better protection against a CDM event compared to conventional approach.

The problem of pin-constrained electrowetting-ondielectric (EWOD) biochips becomes a serious issue to realize complex bio-chemical operations. Due to limited number of control pins and routing resources, additional Printed Circuit Board (PCB) routing layers may be required which potentially raises the fabrication cost. Previous state-of-the-art work has tried to develop a framework that uses a network-flow-based method for broadcast electrodeaddressing EWOD biochips. Nevertheless, greedily merging of electrical pins in previous works is at high risk of producing unroutable design. Routability should have higher priority than pin reduction. While previous works dedicated their effort on pin reduction, we have addressed our attention on routability of broadcast addressing. Experimental results demonstrate that taking routability into consideration can even have higher pin reduction. Viewed in this light, we present ACER, a routability driven clustering algorithm followed by escape routing using integer linear programming that effectively solves both pin merging and routing in broadcast addressing framework. Our proposed algorithm does not greedily focus on pin-reduction. Instead, routability is taken into consideration through agglomerative clustering. Compared to previous state-of-the-art, our proposed algorithm can further reduce required control pins by an average of 13% and route the design using 68% less wirelength.

In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240× speedup.

In this paper, we propose a power density mitigation algorithm at post-placement stage. Our proposed framework first identifies cluster of bins with high temperature, then propagates power density away from high temperature region by balancing regional power density. The problem of balancing regional power density is modeled as a supply-demand problem and solution is obtained with minimal displacement of cells. An analytical temperature profiling algorithm is tightly integrated within the framework to constantly update the temperature profile in response to incremental perturbation to placement. Our proposed approach can effectively reduce maximum temperature compared to previous works on temperature mitigation.

In this paper, we propose a framework that automatically generates a power network based on given placed design and verifies the power network by the commercial tool without IR and Electro-Migration (EM) violations. Our framework integrates synthesis, optimization and analysis of power network. A deterministic method is proposed to decide number and location of power stripes based on clustering analysis. After an initial power network is synthesized, we propose a sensitivity matrix Gswhich is the correlation between updates in stripe resistance and nodal voltage. An optimization scheme based on Sequential Linear Programming (SLP) is applied to iteratively adjust power network to satisfy a given IR drop constraint. The proposed framework constantly updates voltage distribution in response to incremental change in power network. To accurately capture voltage distribution on a given chip, our power network models every existing power stripes and via resistances on each layer. Experimental result demonstrates that our power network analysis can accurately capture voltage distribution on a given chip and effectively minimize power network area. The proposed methodology is experimented on two real designs in TSMC 90nm and UMC 90nm technology respectively and achieves 9%–32% reduction in power network area, compared with the results from modern commercial PG synthesizer.

In this article, we propose a flip-flop merging algorithm based on agglomerative clustering. Compared to previous state-of-the-art on flip-flop merging, our proposed algorithm outperforms that of Chang et al. [2010] and Wang et al. [2011] in all aspects, including number of flip-flop reductions, increase in signal wirelength, displacement of flip-flops, and execution time. Our proposed algorithm also has minimal disruption to original placement. In comparison with Jiang et al. [2011], Wang et al. [2011], and Chang et al. [2010], our proposed algorithm has the least displacement when relocating merged flip-flops. While previous works on flip-flop merging focus on the number of flip-flop reduction, we further evaluate the power consumption of clock tree after flip-flop merging. To further minimize clock tree wirelength, we propose a framework that determines a preferable location for relocated merged flip-flops for clock tree synthesis (CTS). Experimental results show that our CTS-driven flip-flop merging can reduce clock tree wirelength by an average of 7.82% with minimum clock network power consumption compared to all of the previous works.

In this paper, we propose a fast and accurate thermal aware analytical placer. Thermal model is constructed based on Green function with enhanced DCT to generate full chip temperature profile. Unlike other previous thermal aware placers, our thermal model is tightly integrated with a flat force directed placement. A thermal spreading force based on 2D Gaussian model is proposed to reduce maximum on-chip temperature with dynamic hot region size control, optimizing between total half-perimeter wirelength (HPWL) and on-chip temperature distribution. Our thermal model is evaluated by the most recent commercial tool and has an average deviation of 6.5% with 242× speed up. Our placer can reach the same quality compared to Capo and APlace2 with 2–3× speed up. Experiments are tested using ISPD 2005 benchmark with up to 2 million gate design. The results are further evaluated using GSRC Bookshelf Evaluator for total HPWL, and using ICEPAK for temperature distribution. To the best of our knowledge, this is the first thermal-aware placer using analytical thermal model and experimented on large scale design. It takes 6.5 hours to complete entire 2005 ISPD benchmark using our thermal aware placer.

In this paper, an optimization methodology using agglomerative-based clustering for number of flip-flop reduction and signal wirelength minimization is proposed. Comparing to previous works on flip-flop reduction, our method can obtain an optimal tradeoff curve between flip-flop number reduction and increase in signal wirelength. Our proposed methodology outperforms [1] and [12] in both reducing number of flip-flops and minimizing increase in signal wirelength. In comparison with [9], our methodology obtains a tradeoff of 15.8% reduction in flip-flop's signal wirelength with 16.9% additional flip-flops. Due to the nature of agglomerative clustering, when relocating flip-flops, our proposed method minimizes total displacement by an average of 5.9%, 8.0%, 181.4% in comparison with [12], [1] and [9] respectively.