Demo Data from SIGIR 2026 / reviewers in the wild / expert
John Horan
dblp:80/2169
· DBLP profile ↗
6ranked-venue papers
2as first author
0since 2021 · last 2015
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 5 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 2Systems, architecture and hardware · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer graphics and multimedia
1 paper |
Visual content generation and editing · 77% Rendering · 23% | |
| Artificial intelligence
1 paper |
Planning, search and constraint satisfaction · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 4 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Visual content generation and editing › image generation › person image generation
portrait synthesis |
0.1 | 1 | 2008 | A Hybrid Approach to Domino Portrait Generation · AAAI 2008 |
Rendering
non-photorealistic rendering |
0.0 | 1 | 2008 | A Hybrid Approach to Domino Portrait Generation · AAAI 2008 |
Integrated circuit design › analog and mixed-signal circuits
device modeling |
0.0 | 1 | 1989 | Analysis of distributed resistance effects in MOS transistors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989 |
Integrated circuit design › analog and mixed-signal circuits › device modeling
MOSFET modeling |
0.0 | 1 | 1989 | Analysis of distributed resistance effects in MOS transistors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989 |
Methods — techniques the papers use, named apart from their topics
hybrid approach · 0.1constraint satisfaction · 0.1device simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | Data Analytics and Optimisation for Assessing a Ride Sharing System
Vincent Armant, John Horan, Nahid Mabub, Kenneth N. Brown |
IDA | 2 |
| 2009 | Towards Diverse Relaxations of Over-Constrained ModelsabstractIn many interactive decision making scenarios there is often no solution that satisfies all of the user's preferences. The decision process can be helped by providing explanations. Relaxations show sets of consistent preferences and, thus, indicate which preferences can be enforced, while exclusion sets show which preferences can be relaxed to obtain a solution. Many approaches have been proposed to generate relaxations of over-constrained sets of constraints. However, most focus on generating a single relaxation. In this paper we study a variety of heuristic methods for generating diverse sets of relaxations. We show that a heuristic based approach can generate diverse relaxations quickly enough to support user interaction. We also describe a prototype explanation visualisation tool that can help a user navigate over diverse sets of explanations. John Horan, Barry O'Sullivan |
ICTAI | 1 |
| 2008 | A Hybrid Approach to Domino Portrait Generation
Hadrien Cambazard, John Horan, Eoin O'Mahony, Barry O'Sullivan |
AAAI | 2 |
| 2008 | Fast and Scalable Domino Portrait Generation
Hadrien Cambazard, John Horan, Eoin O'Mahony, Barry O'Sullivan |
CPAIOR | 2 |
| 2007 | Generating and Solving Logic Puzzles through Constraint Satisfaction
Barry O'Sullivan, John Horan |
AAAI | 2 |
| 1989 | Analysis of distributed resistance effects in MOS transistorsabstractA method of modeling the distributed source and drain resistance effects in MOS transistors is discussed. Simulations performed using this technique are validated by comparisons with purpose-built structures. The method is then used to examine a problem which arises with the use of a high-temperature interconnect in three-dimensional silicon-on-insulator technologies. The results show how the resistivity of the interconnect affects the performance of the substrate devices of this technology, and the benefits achievable through further development of the existing interconnect technologies are outlined. Finally, the procedure is used to examine the effect of reduced contact size on standard MOS devices, and results wh1ich give general guidelines to the extent of the effect are presented.> John Horan, Colin Lyden, Alan Mathewson, Ciaran G. Cahill, W. A. Lane |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |