In order to achieve satisfactory verification for complicated low-power demands in green products, we propose a verification work reduction methodology. It consists of three step, namely virtual, direct actual, and actual model simulations. Virtual low-power simulation inserts low-power cells, such as isolators or level shifters, virtually and simulates logical behavior for design under test (DUT) based on user-defined power mode. Direct actual low-power simulation replaces behavior models without non-logical pins for some of modules with actual models with non-logical pins, which are Vdd and Gnd, and simulates DUT in mixed level. Actual low-power simulation simulates DUT by using actual models with non-logical pins for all cells and hard macros. We introduce techniques which classify the type of the bugs on which we focus at each verification step and prevent the concerned bugs from leaking to the latter verification step as much as possible. We applied our methodology to an actual chip and could reduce the total simulation period until tape-out by 38.8% and the total chip development period by 10%, compared with the conventional methodology.

A number of haptic devices have recently become available on the commercial market, and these devices are becoming common not only in research but in consumer use as well. In this paper, a new parallel mechanism, referred to herein as DELTA-R (meaning DELTA-Redundant, formerly referred to as DELTA-4) is proposed for a new haptic device having high-quality force display capability and operability. DELTA-R allows three-degree-of-freedom (DOF) translational motions. The key features of DELTA-R, as compared with conventional parallel mechanisms, are redundant actuation, a smaller footprint, a larger working area, and improved access to the end effector. The prototype is equipped with a 3-DOF rotation mechanism, the center of motion of which is located on the wrist position of the operator. An evaluation test of the force display was conducted using a prototype of the proposed mechanism. This paper describes the kinematic design, kinematic modeling, kinematic analysis, prototype implementation, and evaluations.

Nowadays, several haptic devices are commercialized and becoming common not only in research fields but also in consumer use. In this paper, a new parallel link mechanism “DELTA-4” is proposed for a new haptic device within high quality force display capability and operability. DELTA-4 consists of 3 DOF of translational motions. The key features of DELTA-4 comparing with conventional parallel link mechanisms are: a redundant actuation, a wide working area and a small footprint. The prototype is equipped with a 3 DOF of rotation mechanism, which its center of motions is located on the wrist position of an operator. An evaluation test of force display was conducted on a prototype of DELTA-4 mechanism.

In the present paper, we propose a new way of organizing Web search results and of viewing those results passively in the mobile environment which has limited display and limited interaction. Specifically, the system makes Carousel Components, that are composed of image and voice, from Web search result. Each time of user's interaction, the system automatically computes sets of similar, different, more-detailed, and more-abstracted pages, respectively and reorganizes them as carousels. We call this system WebCarousel.

This paper describes a 32-bit CISC superscalar microprocessor designed for high-end embedded applications, such as X-window terminals and printers. To realize high performance of processing a series of memory data such as a frame buffer and a character-string, we have used block-data-transfer and 64-bit processing to improve execution efficiency of multiple-operation instructions of the processor. 16-byte block read/write operations through a 32-bit external data bus have accomplished high bandwidth for DRAM access, even in the case of non-cacheable regions such as a frame buffer. In executing multiple-operation instructions, 64-bit processing has been realized by operating the dual execution circuits for superscalar executions and a 64-bit internal data bus under the control of a very long micro-instruction word. By using these techniques, we have enhanced the frame buffer manipulation performance of this processor 1.5 to 2 times.>