In this paper, we propose a new capacitive boosted buffer technique that can be used in high speed interconnect for ultra-dynamic voltage scaling (UDVS) application with the process variation effect mitigated. The circuit is simple and fully compatible with digital CMOS technology. Implemented in a standard 0.18 μm CMOS technology, the circuit is shown applicable for both sub-threshold circuit and above threshold circuit without the problem of short current. Simulation results demonstrate the conclusion that the proposed new buffer is more robust to load, process, voltage, and temperature (PVT) variations. When applied to a simple H-tree clock network, the proposed buffer can reduce the skew by 5.5x when compared to that of the traditional buffer.

In this paper, we propose some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems. By utilizing local redundancy and inner feedback techniques, the latches and flip-flops can recover from soft errors caused by cosmic rays and particle strikes. The proposed flip-flop can be used as a level shifter without the problems of static leakage and redundant switching activity. Implemented in a standard 0.18- mum technology, the proposed latches and flip-flops show superior performance compared to conventional ones in terms of delay and power while keeping the soft-error-tolerant characteristic. Experimental results show that compared to the traditional built-in soft-error-tolerant D latch, the D-QN delay of the new D latch is 29.1% less than that of the traditional built-in soft-error-tolerant D latch while consuming 16.5% less power as well. The D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional high speed level-converting flip-flop, respectively. In addition, the proposed flip-flop is more robust to soft errors. The critical charge which represents the minimum charge at the D input required to cause an error of the flip-flop can be increased by more than 46.4%. The time window during which the flip-flop will be erroneous caused by single-event upsets at the D input is reduced by more than 22.2%.

Power has become an important concern for nanometer circuit design as well as timing characteristic. In this paper, a novel low power interface circuit design technique was proposed for multiple voltage islands scheme by using output feedback, conditional switch, and pulsed clock technique. The method was applied to new types of flip-flops and combinational logics to eliminate level converters and remove redundant switching activities. Combined with multiple VTH technique, a low clock swing flip-flop is designed to verify our new method. Experimental results show that the leakage power of the new flip-flop can be reduced by an average of 58.14% in standby mode and the total power consumption can be reduced by an average of 55.76% in active mode, while the delay time stays the same

In deep-submicrometer integrated circuits, inductance effects have become increasingly significant, and interconnects are often modeled as transmission lines. An equivalent circuit model, which is called the γd/n model and regularly constructed by two elementary resistance–capacitance–inductance–conductance cells, is proposed for transmission line modeling in this paper. Unlike those moment-matching techniques, the γd/n model is a physical model in nature, and it can be applied to generated high-accuracy, stable, passive, and reduced-order models of transmission lines. In addition, RC(L) interconnect loads are also considered in this paper. Experimental results show that the proposed method can accurately capture the transmission line effect and the capacitive load effect. The waveform obtained by this method differs from that by the exact model in SPICE simulation with the average voltage difference less than 0.9%. For a wide range of interconnect parameters, it has been shown that this method can achieve less than 6% in average error of the 50% delays for both the near-end response and the far-end response.