Multithreading has been promoted as an effective mechanism to hide inter-processor communications and remote data access latencies by quickly switching among a set of ready threads. In this paper, we show that multitreading provides an immunity to the performance variations due to changes in data distributions in a distributed-memory multiprocessor. First, toe propose two performance metrics to quantify the sensitivity of performance to data-locality. Second, we perform a quantitative comparison of data-locality sensitivity with both single-threaded and multithreaded computations. These experiments are performed on a 20-node EARTH-MANNA system. Our results show that not only does a multithreaded computation yields higher performance than the single-threaded version, but also that its performance is more robust (less affected) by variations in data-locality.

Parallel systems supporting multithreading, or message passing in general, have typically used either polling or interrupts to handle incoming messages. Neither approach is ideal; either may lead to excessive overheads or message-handling latencies, depending on the application. This paper investigates a combined approach---Polling Watchdog, where both are used depending on the circumstances. The Polling Watchdog is a simple hardware extension that limits the generation of interrupts to the cases where explicit polling fails to handle the message quickly. As an added benefit, this mechanism also has the potential to simplify the interaction between interrupts and the network accesses performed by the program.We present the resulting performance for the EARTH-MANNA-S system, an implementation of the EARTH (Efficient Architecture for Running THreads) execution model on the MANNA multiprocessor. In contrast to the original EARTH-MANNA system, this system does not use a dedicated communication processor. Rather, synchronization and communication tasks are performed on the same processor as the regular computations. Therefore, an efficient message-handling mechanism is essential to good performance. Simulation results and performance measurements show that the Polling Watchdog indeed performs better than either polling or interrupts alone. In fact, this mechanism allows the EARTH-MANNA-S system to achieve the same level of performance as the original EARTH-MANNA multithreaded system.

High-speed microprocessors need fast on-chip caches in order to keep busy. Direct-mapped caches have better access times than set-associative caches, but poorer miss rates. This has led to several hybrid on-chip caches combining the speed of direct-mapped caches with the hit rates of associative caches. In this paper, we unify these hybrids within a single framework which we call the hybrid access cache (HAC) model. Existing hybrid caches lie near the edges of the HAC design space, leaving the middle untouched. We study a group of caches in this middle region, a group we call half-and-half caches, which are half direct-mapped and half set-associative. Simulations confirm the predictive valve of the HAC model, and demonstrate that, for medium to large caches, this middle region yields more efficient cache designs.>

In this paper, we introduce a user-level threads package called the Threaded CommunicationLibrary which provides primitives to support programs under a multi-threaded program execution model.We present some preliminary experiments compariug the performance of benchmarks using the dual-processor TCL implementation to a single-processor version in which all computation, synchronization, and communication are performed on one processor of a node.Our results indicate that: 1) for applications with highly asynchronous fine-grain communication demands, the dual-processor implementation can effectively overlap communication and computation for faster execution; and 2) with more regular communication requirements, the cache effect ou the computation processor should not be ignored.In some benchmark programs in which the data to be communicated between processors can be kept on the on-chip cache of the computation processor, the single processor version of TC L may yield better performance due to the avoided cache misses which the dualprocessor version encounters.

Data parallel languages based on user-supplied data distribution directives significantly simplify the development of the initial version of a parallel application. However, selection of good data distributions leading to efficient computations is often quite difficult. Therefore, performance debuggers are usually employed to yield insights into effects of data distribution. This paper presents design and implementation of a performance debugger that is specifically targeted to meet the performance debugging requirements of a data-parallel programming model based on user-specified data distributions. The visual interface of the performance debugger provides feedback regarding data distributions amongst processor nodes, data access patterns during program execution, as well as statistical performance data. The feedback provided by the performance debugger is explicitly related back to objects in the programmer's source code.

Dataflow software pipelining was proposed as a means of structuring fine-grain parallelism and has been studied mostly under an idealized dataflow architecture model with infinite resources[9]. In this paper, we investigate the effects of software pipelining under realistic architecture models with finite resources. Our target architecture is the McGill Dataflow Architecture which employs conventional pipelined techniques to achieve fast instruction execution, while exploiting fine-grain parallelism via a data-driven instruction scheduler. To achieve optimal execution efficiency, the compiled code must be able to make a balanced use of both the parallelism in the instruction execution unit and the fine-grain synchronization power of the machine.