VHDL is a critical language for RTL design and is a major component of the $200+ million RTL simulation market. Many users prefer to use VHDL for RTL design as the language continues to provide desired characteristics in design safety, flexibility and maintainability. While VHDL has provided significant value for digital designers since 1987, it has had only one significant language revision in 1993. It has taken many years for design state-of-practice to catch-up to and, in some cases, surpass the capabilities that have been available in VHDL for over 15 years. Last year, the VHDL analysis and standardization group (VASG), which is responsible for the VHDL standard, received clear indication from the VHDL community that it was now time to look at enhancing VHDL. In response to the user community, VASG initiated the VHDL-200x project. VHDL-200x will result in at least two revisions of the VHDL standard. The first revision is planned to be completed next year (2004) and will include a C language interface (VHPI); a collection of high user value enhancements to improve designer productivity and modeling capability and potential inclusion of assertion-based verification and testbench modeling enhancements. A second revision is planned to follow about2 years later. This paper focuses on the 1/sup st/ revision enhancements.

This paper presents a new approach to datapath synthesis based on a problem-space genetic algorithm (PSGA). The proposed technique performs concurrent scheduling and allocation of functional units, registers, and multiplexers with the objective of finding both a schedule and an allocation which minimizes the cost function of the hardware resources and the total time of execution. The problem-space genetic algorithm based datapath synthesis system (PSGA-Synth) combines a standard genetic algorithm with a known heuristic to search the large design space in an intelligent manner. PSGA-Synth handles multicycle functional units, structural pipelining, conditional code and loops, and provides a mechanism to specify lower and upper bounds on the number of control steps. The PSGA-Synth was tested on a set of problems selected from the literature, as well as larger problems created by us, with promising results. PSGA-Synth not only finds the best known results for all the test problems examined in a relatively small amount of CPU time, but also has the ability to efficiently handle large problems.>

Examines the via assignment problem that arises when the single-row routing approach to the interconnection problem is used. Some new complexity results and two new heuristics are obtained. Experimental results establish the superiority of the new heuristics over earlier ones.>

Abstract A front‐end of an electronic CAD synthesis system is described. The synthesis system accepts a behavioural description of a digital system design written in VHSIC Hardware Description Language (VHDL) and produces the physical hardware, at the register transfer level, needed for realizing the specified behaviour. The synthesis system comprises three major subsystems: process‐graph analyser, design representation and the MIMOLA synthesis system. The process‐graph analyser is an optimization and parallelization tool. We show how optimizing techniques used for compilers are adapted to perform a similar optimization function for hardware synthesis. We present techniques that extend the parallelization of the sequential programs concept for doing control state partitioning. The technique is new because of the unique synthesis model that MIMOLA uses. Finally, we show how to integrate these concepts using a suitable intermediate behavioural representation called the process graph.

Abstract We develop a linear time algorithm to determine if a given planar triangulated graph has a rectangular dual.

We develop an Ο(n) algorithm to construct a rectangular dual of an n-vertex planar triangulated graph.