Demo Data from SIGIR 2026 / reviewers in the wild / expert
Sean Rul
dblp:82/5949
· DBLP profile ↗
5ranked-venue papers
2as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 87% Programming languages and type systems · 13% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › parallelization
automatic parallelization |
0.1 | 1 | 2008 | Extracting coarse-grain parallelism in general-purpose programs · PPoPP 2008 |
Compilers and program optimization › parallelization
coarse-grain parallelism extraction |
0.1 | 1 | 2008 | Extracting coarse-grain parallelism in general-purpose programs · PPoPP 2008 |
Processor architecture and microarchitecture
chip multiprocessor |
0.0 | 1 | 2008 | Extracting coarse-grain parallelism in general-purpose programs · PPoPP 2008 |
Methods — techniques the papers use, named apart from their topics
loop analysis · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | The Paralax infrastructure: automatic parallelization with a helping handabstractSpeeding up sequential programs on multicores is a challenging problem that is in urgent need of a solution. Automatic parallelization of irregular pointer-intensive codes, exemplified by the SPECint codes, is a very hard problem. This paper shows that, with a helping hand, such auto-parallelization is possible and fruitful. Hans Vandierendonck, Sean Rul, Koen De Bosschere |
PACT | 2 |
| 2010 | Accelerating Multiple Sequence Alignment with the Cell BE ProcessorabstractThe Cell Broadband Engine (BE) Architecture is a new heterogeneous multi-core architecture targeted at compute-intensive workloads. The architecture of the Cell BE has several features that are unique in high-performance general-purpose processors, most notably the extensive support for vectorization, scratch pad memories and explicit programming of direct memory accesses (DMAs) and mailbox communication. While these features strongly increase programming complexity, it is generally claimed that significant speedups can be obtained by using Cell BE processors. This paper presents our experiences with using the Cell BE architecture to accelerate Clustal W, a bio-informatics program for multiple sequence alignment. We report on how we apply the unique features of the Cell BE to Clustal W and how important each is in obtaining high performance. By making extensive use of vectorization and by parallelizing the application across all cores, we demonstrate a speedup of 24.4 times when using 16 synergistic processor units on a QS21 Cell Blade compared to single-thread execution on the power processing unit. As the Cell BE exploits a large number of slim cores, our highly optimized implementation is just 3.8 times faster than a 3-thread version running on an Intel Core2 Duo, as the latter processor exploits a small number of fat cores. Hans Vandierendonck, Sean Rul, Koen De Bosschere |
Comput. J. | 2 |
| 2010 | A profile-based tool for finding pipeline parallelism in sequential programs
Sean Rul, Hans Vandierendonck, Koen De Bosschere |
Parallel Comput. | 1 |
| 2008 | Experiences with Parallelizing a Bio-informatics Program on the Cell BE
Hans Vandierendonck, Sean Rul, Michiel Questier, Koen De Bosschere |
HiPEAC | 2 |
| 2008 | Extracting coarse-grain parallelism in general-purpose programsabstractWhile the chip multiprocessor (CMP) has quickly become the predominant processor architecture, its continuing success largely depends on the parallelizability of complex programs. In the early 1990s great successes were obtained to extract parallelism from the inner loops of scientific computations. In this paper we show that significant amounts of coarse-grain parallelism exists in the outer program loops, even in general-purpose programs. This coarse-grain parallelism can be exploited efficiently on CMPs without additional hardware support. Sean Rul, Hans Vandierendonck, Koen De Bosschere |
PPoPP | 1 |