This paper presents a system-on-chip (SoC) architecture for an active implantable microsystem that combines electrical recording with optogenetic stimulation for closed-loop neuromodulation. The SoC is designed to support a 4-shank optrode (opto-electrode) fork with 8 differential recording channels (0.1-5000Hz bandwidth, 10mVpp range, 12-bit resolution) to observe neural signals on electrodes and 32 driver circuits (2mA range, 6-bit current resolution with μs timing resolution) for microLED optical stimulation. Each SoC additionally integrates diagnostic instrumentation to measure electrical resistance across any of its I/O lines. The SoC features a custom 4-wire interface that provides power and data communication across multiple chips using a shared bus allowing for multiple forks to be stacked to form two dimensional optrode arrays. Each chip has an independent controller that receives, interprets and executes commands, and can transmit neural data while simultaneously controlling LED outputs. The circuit is implemented in a 180nm CMOS process, with each chip occupying a 5mm×2.45mm silicon footprint, designed specifically to mount on the base of the silicon optrode fork.

This paper presents an application specific integrated circuit (ASIC) for use in a three-dimensional microchannel neural interface. The device is assembled with seven stacked ASICs with silicone microchannels instrumented in between. Each ASIC comprises tripolar electrodes for seven channels allowing recording or stimulation from any one of the 49 microchannels. The ASIC is implemented in 0.35μm high-voltage CMOS technology and occupies an active area of 4 mm2. The device has been tested demonstrating recording of 1 mV signals, and current controlled stimulation in the range of 5 μA to 500 μA (with 40 V compliance) and up to 50 kHz stimulation frequency. The device overcomes limits on numbers of connected microchannels in previous designs.

There remains a need for satisfactory integrated sensors that can monitor humidity inside small active implanted devices in which delicate electronics are operating. This paper describes a simple capacitance-to-digits readout circuit for a capacitive humidity sensor for ultra-small medical implants. The proposed readout circuit provides a larger dynamic range than conventional capacitance readout circuits by removing the parasitic capacitance from the measured capacitive input. The circuit was designed in XFAB's 0.6-μm CMOS technology and provides 1 % resolution in measuring relative humidity.

This paper presents a fully implantable multi-channel neural prosthesis for epidural stimulation. The prosthesis features three telemetry-operated independent stimulators providing in total eighteen stimulation channels. The stimulator circuits were implemented in a 0.6-μm CMOS technology. The prosthesis is protected in a hermetically sealed ceramic enclosure and encapsulated in medical grade silicone rubber. In-vitro measured results with electrodes in saline are presented.

A fully implantable multi-channel neural prosthesis for epidural stimulation will be demonstrated. The prosthesis features three telemetry-operated independent stimulators providing in total eighteen stimulation channels. The stimulator circuits were implemented in a 0.6-μm CMOS technology. The prosthesis is protected in a hermetically sealed ceramic enclosure and encapsulated in medical grade silicone rubber for long-term implantation. During the live demonstration in-vitro tests with electrodes in saline will be performed with the prosthesis operated wirelessly from a remote computer.

A high voltage supply is necessary for implantable stimulators that need to deliver high stimulus current to load tissue and overcome large electrode impedance. A constantly high supply voltage results in unnecessary power wastage in low-voltage stimulation and is potentially dangerous at the neural tissue interface. This paper presents the authors' recent progress in developing a stimulation system with self-adapting supply based on the previous Active Books system. The improved design is able to measure the peak electrode voltage on any specified anode and feed back the information to a central hub unit. If the peak electrode voltage is significantly lower than the current supply voltage, the adjustable voltage regulator in the hub will issue a lower but high enough supply voltage to power up the stimulator chip. The circuit has been designed and simulated in a 0.6-μm HV CMOS process.

A persistent-if less glamorous—challenge in hospitals lies in the day-to-day work of moving and lifting patients with impaired mobility. This is a challenge intensified by our burgeoning aging population, the obesity epidemic, and our aging healthcare workforce. During manual patient handling, the predominant risk of staff injury is excessive back and shoulder loading. A mobile robotic nurse assistant (RoNA) is highly desired to enhance the efficacy and quality of care that nurses and their paraprofessional staff can provide. Such an assistant could improve a nurse's working conditions by off-loading some of his or her most physically demanding duties, thereby reducing the potential for self-injury or injury to the patient. Hstar Technologies is developing a revolutionary RoNA system that provides physical assistance to nurses in a hospital ward. The design of RoNA is a safe and robust system that works effectively in a hospital environment under direct and telepresence control by a nurse or physician. RoNA has a humanoid design featuring bimanual dexterous manipulators that employ a series-elastic-actuation (SEA) system. These electric actuators provide manipulator compliance, safety, flexibility and the strength to lift patients weighing up to 300lbs. RoNA also features an innovative humanoid upper torso, a unique mobile platform with holonomic drive and posture stability enhancement, intelligent navigation control with 3D sensing and perception capability, an intuitive and innovative human-robot interaction control interface, and a highly integrated plan for healthcare system assembly. We anticipate that robotic maneuvering assistants would increase job satisfaction, reduce lifting-related injuries, and extend the years of effective service nurses could render in hospitals. These effects would reduce hospital costs and ameliorate problems posed by the shortage of nursing staff.

The aim of this paper is to compare three recording methods for interference rejection from tripolar nerve cuffs by testing in a saline-filled tank. The three methods were: the quasi-tripole (QT), the modified-quasi-tripole (mQT) and adjusted true tripole (aTT). When the interfering electric field that surrounds the cuff is solonoidal and coaxial with the cuff, the mQT allows the interference that happens to be present due to asymmetry to be neutralized at one frequency, and reduced across the ENG band. The aTT is better in this situation, allowing almost complete neutralization at all frequencies. However, when the electric field is altered after adjustment, the interference was greater for the aTT than the mQT. In an implant, the interference is likely to come from nearby muscles and the fields will be continuously changing as the action potentials propagate. Therefore, it is likely that mQT will be better than the aTT.

This paper describes the stimulation management unit for a multichannel vestibular neural prosthesis. The unit is designed as part of a stimulator ASIC in the implantable subsystem of the prosthesis. This digital unit provides the stimulator ASIC the ability to generate biphasic current pulses at specified amplitude, duration and pulse rate to drive electrodes in the semicircular canals. The circuit was implemented in 0.6-μm CMOS technology and post-layout simulations are presented to show its operation.

We propose a novel dual-mode neural stimulator circuit. For stimulation requiring small or medium amount of charge, the stimulator supplies a constant current to the stimulation load in the same way as any standard current-mode stimulator. For high-charge stimulation applications, the stimulator supplies a variable stimulus current, depending on the voltage available across the current generator circuit. By adjusting the bias current accordingly, the stimulator maintains a high output impedance, independent of the stimulus current and the load voltage at the time. The total stimulus charge from the proposed stimulator is theoretically as high as voltage-mode stimulators. Simulated results using a 0.6-μm CMOS process are presented. At low stimulus current, the output impedance of the proposed stimulator circuit is at least six times higher than a conventional current-mode generator with constant bias current.

We present a current generator circuit which supplies two anodic currents for tripolar nerve stimulation. Depending on applications and the more convenient method of adjustment, the difference of the two anodic currents can be programmed using either of the two different modes. The reference current circuit in the current generator utilizes a gate-drain tied depletion transistor working in the triode region as the degenerating resistor in the Beta-multiplier topology. The negative temperature coefficient of the depletion transistor reduces the total sensitivity of the output current to temperature variation. The proposed current generator circuit is also stable over a wide range of supply voltages. Simulated results using a 0.6-μm CMOS process are presented. The temperature coefficient and power supply rejection ratio of the current generator are less than 0.06%/°C and 2%/V, respectively.

Recording neural information using implanted cuff electrodes in a tripolar arrangement is affected by myoelectric interference present at the implantation site. The performance of the recently proposed mQT was suboptimal in that tuning was required to compensate for such interference. In this work we present an improvement where interference in the mQT is removed by modeling the impedance profile of our electrodes. Simulation data show that by employing this “adaptive” approach, a 33% imbalance in the axial resistances when the interference is of 10 mV at 500 Hz and 10 kHz, results in an interference breakthrough that is about 7230 and 100 times less, respectively, at the amplifier's output.

Many indoor robotics systems use laser rangeflnders as their primary sensor for mapping, localization, and obstacle avoidance. The cost and power of such systems is a major roadblock to the deployment of low-cost, efficient consumer robot platforms for home use. In this paper, we describe a compact, planar laser distance sensor (LDS) that has capabilities comparable to current laser scanners: 3 cm accuracy out to 6 m, 10 Hz acquisition, and 1 degree resolution over a full 360 degree scan. The build cost of this device, using COTS electronics and custom mechanical tooling, is under $30.

An integrated amplifier for electroneurogram (ENG) recordings from tripolar cuff electrodes is described. The amplifier is dedicated to urinary incontinence and other functional electrical stimulation (FES) applications. To remove myoelectric (EMG) interference a parallel RC network is used to balance the electrode impedances in the quasi-tripole amplifier configuration. The various ENG amplifier settings, such as resistance and capacitance trimming for the neutralization RC network, amplifier gain and filter cut-off frequencies, are controlled by an external microcontroller which communicates with the embedded SPI (Serial Port Interface) block in the amplifier. By this topology control of the ENG amplifier is executed in software allowing for the system parameters to be re-configured after implantation. The analog system blocks and details of the SPI logic are described. The amplifier was fabricated in a 3-V 0.35-mum BiCMOS process technology and preliminary measured results are reported. Input signals as low as 1muV can be reliably detected. The amplifier occupies an area of 1.5mm2and consumes about 1.4mW when configured to detect sub-microvolt neural signals.

There is a great demand to reduce the volume of implantable multi-channel stimulators for functional electrical stimulation applications. Miniaturization is currently limited by the size of the large off-chip blocking capacitors that are required for safety. This paper describes a fail-safe stimulator output stage circuit utilizing the principle of high-frequency current-switching, which allows the blocking capacitors to be integrated on-chip. The proposed circuit is based on the bridge rectifier circuit, hence fully utilizing the bidirectional current through the blocking capacitor. The approach has been verified by post-layout simulations in a 1 μm CMOS SOI technology.

The prime concern in the design of biomedical implants is safety. This paper addresses several safety features and proposes a new scheme to transmit power and data from the central implant to the stimulator "pods" while maintaining failsafe operation. The proposed scheme demultiplexes the stimulation command close to the electrodes and uses three wires in total to provide power and data to all stimulator "pods" from the central implant. Thus, it greatly reduces the number of wires routed to the stimulation sites and is able to stimulate more stimulator "peas". The circuit used to recover the power is shown, utilizing the three wires as the only inputs. The power recovery circuit features a varactor as the storage capacitor which gives a faster pumping speed than a linear capacitor. The idea is verified with circuit simulations in a 0.6μm CMOS technology. The proposed scheme ensures that in the event of cable failure, the current will be charge-balanced, thereby avoiding the generation of harmful electrochemical products.

The use of blocking capacitors in the output stages of implantable stimulators for functional electrical stimulation (FES) applications, is common practice for safety reasons. However, these capacitors tend to dominate the implant volume. This paper describes a stimulator output stage circuit which overcomes this limitation. The circuit features a novel capacitor reduction technique for implant miniaturization, and a simple failure-checking mechanism for enhanced reliability. The approach was verified by simulations in a 0.35 mum CMOS technology