To date, commercial industrial robots only provide multi-robot coordination for their own fleet of robots and treat robots from other vendors as general obstacles. The ability to enable robots from different vendors to co-exist in the same space is crucial to prevent vendor lock-in. We present the first decentralized system that achieves coordination between a heterogeneous fleet of black box robots for which the internals of the navigation stack are presumed unmodifiable. Our system, which we call CODAK, achieves the coordination by relying on minimum set of interfaces that are commonly available on most industrial and service robots. For each robot, CODAK uses a trained recurrent neural network to anticipate collisions from externally observable metrics. Anticipated collisions are avoided using a simple, but yet effective, concurrency control scheme. We run a series of experiments in simulation and with real robots to demonstrate CODAK’s ability to enable safe navigation in different environments. We also experimentally compare CODAK with previously published white-box solutions to evaluate the penalty of black-box constraint.

We study the training performance of ROS local planners based on Reinforcement Learning (RL), and the trajectories they produce on real-world robots. We show that recent enhancements to the Soft Actor Critic (SAC) algorithm such as RAD and DrQ achieve almost perfect training after only 10000 episodes. We also observe that on real-world robots the resulting SACPlanner is more reactive to obstacles than traditional ROS local planners such as DWA.

Mobile Edge Computing (MEC) has received much attention from the research community in recent years. A significant part of the published work has studied the telecom-centric MEC architecture, which assumes that the computing resource is located at the edge of the mobile access network (e.g., the Evolved Packet Core or ePC), typically at the first aggregation level. Many of these studies make a silent assumption that the latency at this stage of the network is negligible. We show not only that this assumption is false, but that in some common cases the latency of the first aggregation stage dominates the end-to-end latency. We further show that common probing metrics can easily fail when used to select the service site for an application and discuss possible improvements to server-selection reliability.

We describe and evaluate a software-only implementation of a novel mechanism for accessing and streaming GPU-rendered content from the cloud to low-end user devices. The unique properties of our implementation enable the trivial cloud-deployment of graphics-intensive applications, even ones that were not originally intended to run in the cloud. We achieve this goal by creating virtual GPU nodes that appear to the application like hardware devices, but that do not incur the overhead of virtualization. The low-level access to the frame buffer maximizes the number of applications that work out-of-the-box without the system imposing any specific display manager or windowing system.

We present a compression algorithm and a streaming protocol designed for streaming of computer-desktop graphics. The encoder has low memory requirements and can be broken into a large number of independent contexts with a high degree of data locality. The encoder also uses only simple arithmetic, which makes it amenable to hardware or highly parallel software implementation. The decoder is trivial and requires no memory, which makes it suitable for use on devices with limited computing capabilities. The streaming protocol runs over UDP and has its own unique error recovery mechanism specifically designed for interactive applications.

We describe the design, implementation, and experimental evaluation of a clock recovery algorithm suitable for synchronization over a packet-based metro-area network (MAN) using the Precision Time Protocol (PTP). The algorithm consists of a packet-based phase error estimator and a phase-locked loop (PLL). The loop is augmented with a step detector that detects discontinuities in the packet arrival process due to route or network load changes, and a congestion detector that filters out unusable samples. The PLL requires a number of interesting tradeoffs that are specific for a high noise environment, while the congestion and step detector are non-traditional mechanisms specifically designed to deal with the peculiarities of a packet network.

We analyze the statistical properties of slope estimates obtained from linear regression with sample-minimum Erlang variates. The sample-minimum of sequential blocks has the effect of introducing non-uniform time samples. It is shown that this non-uniformity has negligible effect on the slope estimate variance, but introduces a spurious low-frequency component in the power spectrum, which may be detrimental for ultra-low-bandwidth tracking applications. The analysis shows that this effect can be moderated by choosing a sufficiently large number of sample-minimum output samples in the linear regression. These results are useful, for example, in clock synchronization over packet networks, where the random variates model packet arrival times.

We consider pipelined architectures of packet processors consisting of a sequence of simple packet-processing modules interconnected by first-in first-out buffers. We propose a new model for describing their function, an automated synthesis technique that generates efficient hardware for them, and an algorithm for computing minimum buffer sizes that allow such pipelines to achieve their maximum throughput. Our functional model provides a level of abstraction familiar to a network protocol designer; in particular, it does not require knowledge of register-transfer-level hardware design. Our synthesis tool implements the specified function in a sequential circuit that processes packet data a word at a time. Finally, our analysis technique computes the maximum throughput possible from the modules and then determines the smallest buffers that can achieve it. Experimental results conducted on industrial-strength examples suggest that our techniques are practical. Our synthesis algorithm can generate circuits that achieve 40 Gb/s on field-programmable gate arrays, equal to state-of-the-art manual implementations, and our buffer-sizing algorithm has a practically short runtime. Together, our techniques make it easier to quickly develop and deploy high-speed network switches.

Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the features of the system. We propose a high-level synthesis technique for a new model for representing packet editing functions. Experiments show our circuits achieve a throughput of up to 40Gb/s on a commercially available FPGA device, equal to state-of-the-art implementations.

We describe an implementation of the physical layer circuit for 100Mb/s optical Ethernet using an FPGA device with embedded high-speed serial transceivers. The design is the foundation for implementing a dual-speed 100/1000 Mb/s Ethernet system in which all components except the optical ones are implemented in an FPGA. The low-speed mode is outside the transceiver's nominal range, so the PLL circuit in the receiver cannot reliably lock to the received clock. We solve the problem by using the data recovery technique known as blind oversampling. The design can easily be adapted to implement other transmission systems that may put the operating point of the transceiver outside its nominal range, extending the scope of applications in which "FPGA to the optics" approach is viable.

The goals of performance and flexibility are often at odds in the design of network systems. The tension is common enough to justify an architectural solution, rather than a set of context-specific solutions. The Programmable Protocol Processing Pipeline (P4) design uses programmable hardware to selectively accelerate protocol processing functions. A set of field-programmable gate arrays (FPGAs) and an associated library of network processing modules implemented in hardware are augmented with software support for function selection and composition, and applied to processing-intensive portions of a user-programmable protocol stack. The system is sufficiently flexible to support protocol stacks that are dynamically altered in reaction to changing network conditions or user needs.The P4 can be transparently inserted into a conventional protocol architecture, such as that of TCP/IP. This experimental demonstration shows that the P4's programmability can be used to significantly improve the performance of TCP/IP under operating conditions where the protocol would perform poorly without augmentation. Generalizing from these experiments, the P4 is shown to have many applications as an open platform for implementing adaptive and programmable networks, and has illustrated new security issues that arise in FPGA-based architectures.The P4 and closely-related systems, such as network processors, are attractive architectural solutions to balancing performance and flexibility.

Service providers are showing strong interest in building all-Ethernet public metropolitan networks that would compete with (and eventually replace) the existing network infrastructures based on SONET, Frame Relay, ATM and similar technologies. The main driving factor is the cost, as Ethernet-based technology is typically cheaper than any others available on the market. Despite successful initial laboratory and field deployment tests, there are still many unresolved issues related to metropolitan-scale Ethernet, such as the appropriateness of a spanning tree algorithm, broadcast flooding and MAC address table explosion in core switches. This paper focuses on the problem of MAC address table explosion by introducing a hierarchy into the address space, through Ethernet-inside-Ethernet packet encapsulation. The encapsulation allows core switches to be standard Ethernet switches, while the edge switches implement concepts presented in this paper. The proposed concept is thus transparent to the existing infrastructure and thereby allows building the network using readily available low-cost layer-2 switches.