Gyu Tae Jang

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2ranked-venue papers

0as first author

0since 2021 · last 1995

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

2 papers

Embedded and real-time systems · 62% Electronic design automation · 30% Memory systems · 8%

Topics — the 7 heaviest of 7, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Embedded and real-time systems worst-case execution time analysis	2	1995	An Accurate Worst Case Timing Analysis for RISC Processors · IEEE Trans. Software Eng. 1995 An Accurate Worst Case Timing Analysis Technique for RISC Processors · RTSS 1994
Electronic design automation › timing analysis pipeline and cache timing analysis	1	1995	An Accurate Worst Case Timing Analysis for RISC Processors · IEEE Trans. Software Eng. 1995
Embedded and real-time systems real-time scheduling	1	1995	An Accurate Worst Case Timing Analysis for RISC Processors · IEEE Trans. Software Eng. 1995
Embedded and real-time systems › real-time scheduling › worst-case analysis worst-case execution time estimation	1	1995	An Accurate Worst Case Timing Analysis for RISC Processors · IEEE Trans. Software Eng. 1995
Electronic design automation › hardware verification and test › timing verification pipeline timing analysis	1	1994	An Accurate Worst Case Timing Analysis Technique for RISC Processors · RTSS 1994
Memory systems cache	1	1994	An Accurate Worst Case Timing Analysis Technique for RISC Processors · RTSS 1994
Memory systems › cache › CPU cache instruction cache	1	1994	An Accurate Worst Case Timing Analysis Technique for RISC Processors · RTSS 1994

Methods — techniques the papers use, named apart from their topics

timing schema · 0.0static analysis · 0.0

Year	Publication	Venue	Position
1995	An Accurate Worst Case Timing Analysis for RISC Processors abstract An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. The paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach.> Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim	IEEE Trans. Software Eng.	3
1994	An Accurate Worst Case Timing Analysis Technique for RISC Processors abstract An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, this paper proposes extensions of the original timing schema (Shaw, 1989) where the timing information associated with each program construct is a simple time-bound. We associate with each program construct what we call a WCTA (Worst Case Timing Abstraction), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time-bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analyses for a pipelined processor. Our results show that up to 50% tighter WCET bounds can be obtained by using the revised timing schema.> Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Chong-Sang Kim	RTSS	3