A new VLSI CAD environment considering stochastic behavior of MTJ devices is proposed for the evaluation of not only the performance but also the reliability of MTJ/MOS-hybrid logic LSI. The proposed simulator allows users to support the design of MTJ/MOS-hybrid LSI by RTL/gate-level hardware description, whose simulation considering stochastic switching behavior of MTJ device can be done by analog-mixed-signal simulation with de-facto standard EDA tools. Through the design of a nonvolatile logic LSI based on a general purpose 32-bit microprocessor, the impact of the proposed design flow is demonstrated.

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable simulation results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, that considerably influence the operation margin and power dissipation. It can also accelerate the simulation speed, which makes it possible to simulate three times or more large-scale circuits than when a conventional macro-model is used.

This paper describes a new technique for 3-terminal regulators to adjust the output voltage level without additional terminals or extra off-chip components. By applying a serial control pattern using the intermediate voltage level between the supply voltage and the regulator output, the adjustment data in the internal nonvolatile memory are safely updated without noise disturbance. In an on-board test with a chip fabricated using a 0.35-¿m standard CMOS process, we confirm successful output voltage adjustment with sub-10mV precision.

A practical microprogram ROM BIST (built-in self-test) scheme suitable for LSI memories is proposed. This BIST can be used to install N-pattern and N/sup 2/-pattern test procedures, using BIST circuits with 12-word*10-b and 16-word*16-b ROMs, respectively. As a practical test procedure, a data retention test, in which BIST circuits with an 8-word*11-b ROM were used, was investigated. BIST circuit area overheads for the above three test patterns for 16-Mb DRAMs are less than 1%, 2%, and 1.5%, respectively. A testing method for the BIST circuits themselves, with no special BIST circuit overhead, is also proposed for more practical applications. The measured operational margin for a 16-Mb DRAM using the BIST showed a good agreement with that using an LSI tester.>