This article proposes a Bayesian learning driven automated embedded memory design methodology that aims to minimize leakage current, minimize power, and maximize performance while meeting predefined constraints. To achieve this objective effectively, we present an automatic tool that leverages a reference initial circuit design to generate a diverse set of schematic and layout options for logic-equivalent circuit variants and various transistor threshold voltage (Vth) modifications, while ensuring compliance with design rules. Subsequently, leveraging the range of circuit options generated, Bayesian optimization is employed not only to identify optimal circuit parameters but also to select the most appropriate circuit topology and individual transistor$V_{th}$to attain the desired design objectives. TSMC 28 nm process simulation results demonstrate the proposed methodology reducing power by 26.28%–46.44%,$T_{\mathrm { access}}$by 25.60%–42.29%, and leakage current by 22.73%–50.11% compared to the compiler-generated design, with a runtime of 10–40 h.

In this paper, we present a Bayesian Optimization (BO)-based methodology for optimizing SRAM design across various configurations while meeting stringent constraints in different Process, Supply voltage, and Temperature (PVT) corners. Our method automatically extracts critical design parameters for power reduction and accelerates optimization using a BO-based approach that suggests multiple points. Additionally, our method efficiently identifies the worst PVT corners, minimizing the number of simulations by considering constraints and utilizing cubic spline interpolation to simultaneously provide optimal circuits for various size instances. By applying our approach, we achieved a significant reduction in dynamic power by 10.24% to 28.55%, access time by 1.76% to 38.16%, and cycle time by 1.20% to 27.39% across all corners while satisfying all constraints. Additionally, assuming our approach is used to optimize all size instances that can be generated by a commercial compiler, the required runtime is reduced by 96.65% to 99.87% compared to using conventional Bayesian Optimization.

This paper presents SRAM design methodology that aims to minimize power consumption and/or maximize performance while meeting predefined constraints through Bayesian optimization (BO). The BO process utilizes sigmoid utility functions to consider the constraints. It also uses a power and performance prediction model based on linear regression, as well as a Gaussian process model accumulation to enable efficient optimization of SRAMs with arbitrary capacity. Moreover, the implementation of automatic layout adjustment enables fully automated optimization without requiring manual layout modifications, allowing for more accurate and efficient optimization process that based on post-layout simulations. Simulation results of TSMC 28nm process show that the proposed methodology reduces 6.9%-17.9% of dynamic power and 0.3%–20.3% of access time compared to the design generated by the commercial compiler. Simulation result spend 10–40 hours and there is no compromising other circuit performance metrics.

Boseop Kim, HyoungSeok Kim, Sang-Woo Lee, Gichang Lee, Donghyun Kwak, Jeon Dong Hyeon, Sunghyun Park, Sungju Kim, Seonhoon Kim, Dongpil Seo, Heungsub Lee, Minyoung Jeong, Sungjae Lee, Minsub Kim, Suk Hyun Ko, Seokhun Kim, Taeyong Park, Jinuk Kim, Soyoung Kang, Na-Hyeon Ryu, Kang Min Yoo, Minsuk Chang, Soobin Suh, Sookyo In, Jinseong Park, Kyungduk Kim, Hiun Kim, Jisu Jeong, Yong Goo Yeo, Donghoon Ham, Dongju Park, Min Young Lee, Jaewook Kang, Inho Kang, Jung-Woo Ha, Woomyoung Park, Nako Sung. Proceedings of the 2021 Conference on Empirical Methods in Natural Language Processing. 2021.

ABSTRACT In general, attackers carry out scanning or probing against a certain network when they start to attack their victims. Because of this, darknet is very useful to observe the scanning activities of attackers who want to find their victims that have security vulnerabilities in operating systems, applications, services, and so on. Thus, by observing and analyzing darknet traffic, it is able to obtain an insight into malicious activities that are happening on the Internet and to identify potential attackers who sent attack packets to the darknet. However, darknet has a fatal limitation that most of the darknet traffic has no payload data. This means that we cannot collect the real attack codes from the original darknet traffic. To cope with this problem, we propose a security monitoring and response model to analyze cyber threats trend and to trace potential attackers based on darknet traffic. We have evaluated the proposed model using one /24 darknet IP addresses and TMS alerts that were obtained from TMS. The experimental results provided the statistical information of all the incoming darknet traffic so that we could obtain the global cyber threats trend. Furthermore, the experimental results demonstrated that we could obtain malicious attack patterns and attack codes that were not detected by TMS. Copyright © 2013 John Wiley & Sons, Ltd.

A larger amount of works has been reported for forward link CDMA scheduling compared to its reverse link case. In this paper, we propose generalized proportional fair (GPF) scheduling algorithms for uplink CDMA packet services, which have the ability to control the degree of fairness (DoF). We first establish a framework for GPF scheduling in wireless networks which render a GPF scheduling as a well-established optimization problem. For uplink CDMA, it is known that the rate sum maximization is achieved when the best K users in terms of channel condition transmit simultaneously. Based on this principle and the proposed GPF framework, we propose two GPF packet scheduling algorithms for uplink CDMA. Performance of our algorithms is verified through simulations.

Radio frequency identification (RFID) is a technology that recognizes information and circumference environment from tags attached to objects via wireless technology, and provides various services such as location tacking, supply chain management. The mobile RFID technology which uses this RFID technology gives mobility to the RFID leader and makes it possible to exchange information between the users and objects whenever or wherever it is needed. The KT introduced the portable Internet service (WiBro) into commercial service as a new growth engine. WiBro is the wireless Internet service which enables a high speed Internet even while moving. Based on WiBro, Korea Telecom (KT) is also developing a new concept WiBro RFID service, combining the WiBro network and the mobile RFID. In this paper, we introduce a mobile RFID service platform and some prototype services based on wireless broadband (WiBro) network.