Highly scaled indium phosphide (InP) heterojunction bipolar transistor (HBT) technologies have been demonstrated with maximum frequencies of oscillation ( f max) of >1 THz and circuit operation has been extended into the lower end of the terahertz (THz) frequency band. InP HBTs offer high radio-frequency (RF) output power density, millivolt (mV) threshold uniformity, and high levels of integration. Integration with multilevel thin-film wiring permits the realization of compact and complex THz monolithic integrated circuits (TMICs). Circuit results reported from InP HBT technologies include: 200-mW power amplifiers at 210 GHz, 670-GHz amplifiers and fundamental oscillators, and fully integrated 600-GHz transmitter circuits. We review the state of the art in THz-capable InP HBT devices and integrated circuit (IC) technologies. Challenges in extending transistor bandwidth and in circuit design at THz frequencies will also be addressed.

Analog-to-digital converters (ADCs) with high sampling rates and output resolution are required for the design of mostly digital transceivers in emerging multi-Gigabit communication systems. A promising approach is to use a time-interleaved (TI) architecture with slower sub-ADCs in parallel, but mismatch among the sub-ADCs, if left uncompensated, can cause error floors in receiver performance. Conventional mismatch compensation schemes typically have complexity (in terms of number of multiplications) that increases with the desired resolution at the output of the TI-ADC. In this paper, we investigate an alternative approach, in which mismatch and channel dispersion are compensated jointly, with the performance metric being overall link reliability rather than ADC performance. For an OFDM system, we characterize the structure of mismatch-induced interference, and demonstrate the efficacy of a frequency-domain interference suppression scheme whose complexity is independent of constellation size (which determines the desired resolution). Numerical results from computer simulation and from experiments on a hardware prototype show that the performance with the proposed joint mismatch and channel compensation technique is close to that without mismatch. While the proposed technique works with offline estimates of mismatch parameters, we provide an iterative, online method for joint estimation of mismatch and channel parameters which leverages the training overhead already available in communication signals.

Time-interleaved (TI) analog-to-digital converters (ADCs) are a promising architecture for realizing the highspeed ADCs required to implement "mostly digital" receivers for emerging multiGigabit communication systems. Mismatch between the parallel ADCs comprising a TI-ADC is a fundamental performance bottleneck. While there exist mismatch correction techniques for generic applications of ADC, we illustrate in this paper that mismatch compensation can be subsumed within the overall receiver design for communication applications. We consider an orthogonal frequency division multiplexing (OFDM) link with TI-ADC used after downconversion. We show that mismatch results in frequency selective interference across subcarriers that can significantly degrade the performance of a standard OFDM receiver. However, this performance degradation can be alleviated significantly by joint channel and mismatch estimation and compensation, leveraging already available training or pilot sequences. This eliminates the necessity for dedicated hardware for mismatch correction. Specifically, we present an algorithm for estimating the channel gains and the mismatch, followed by low-complexity linear equalization to suppress the inter-subcarrier interference resulting from the mismatch. Our simulations show that the error floor due to mismatch-generated interference can be eliminated, permitting bandwidth-efficient operation with large constellations.

Calibration of sub-converter mismatches is a challenging task for high-performance time-interleaved analog-to-digital converters (TIADC). Presently known blind correction methods can remove static gain and sampling time mismatches. However, actual subconverters significantly deviate from a simple gain-timing model, and the resulting modeling error strictly limits maximum output signal-to-noise ratio achievable. Generalized mismatch modeling is, therefore, necessary to break the limitation of gain-timing model. In this paper, we propose a blind method for correcting generalized mismatch errors for M=2 TIADC, which is the first in the literature to the authors' knowledge. Cyclostationary spectral analysis shows that unique identification is possible in most practical cases. Simulation results show significant performance improvement by the proposed generalized correction method.

The authors present a statistics-based blind calibration technique for nonlinear memory errors in amplifier-sharing pipelined ADCs. The proposed method is fully digital and simple to implement. It detects memory errors in normal operation without system suspension for calibration. No special calibration signal or analog circuitry is necessary. Algorithm description and simulation results are presented. The proposed technique improves the power efficiency of pipelined ADCs by enabling sharing of low-gain operational amplifiers.

Time-interleaved analog-to-digital converters (TIADC) require mismatch calibration to achieve high signal-to-noise ratios. In this paper, we present a new blind technique for M=2 TIADC's with following properties: (1) correction of general mismatches as well as static gain and timing error, (2) unique multi-parameter identification under realistic assumptions, and (3) analytic error measure and gradient. The proposed method overcomes the limitation of traditional gain-timing mismatch model. Time-frequency transformation is eliminated by analytic approach, enhancing efficiency.

We report experimental verification of the previously proposed blind method of correcting gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter (TIADC). The experimental setup allows for two different M=2 TIADC configurations with 14-bit resolution and 200-MHz overall sampling rates. Mismatch parameters are estimated by the blind algorithm with representative narrowband and wideband signals. The spurious-free dynamic range (SFDR) performance is then evaluated by using sinusoids. We discuss performance gain, as well as the limitations of the proposed blind algorithm when applied to real world analog-to-digital (A/D) converters.