Demo Data from SIGIR 2026 / reviewers in the wild / expert
Jinquan Dai
dblp:85/4336
· DBLP profile ↗
13ranked-venue papers
6as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 8 · 2 first-authorComputer networks · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-authorDatabases, data management, data science and information retrieval · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
6 papers |
Cloud and datacenter computing · 61% Distributed systems · 21% Processor architecture and microarchitecture · 11% | |
| Software engineering, system software, and programming languages
2 papers |
Compilers and program optimization · 67% Concurrent programming · 33% |
Topics — the 20 heaviest of 20, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cloud and datacenter computing
virtualization |
0.3 | 2 | 2014 | HYVI: A HYbrid VIrtualization Solution Balancing Performance and Manageability · IEEE Trans. Parallel Distributed Syst. 2014 ReNIC: Architectural extension to SR-IOV I/O virtualization for efficient replication · ACM Trans. Archit. Code Optim. 2012 |
Cloud and datacenter computing › virtualization
hardware-assisted virtualization |
0.2 | 1 | 2014 | HYVI: A HYbrid VIrtualization Solution Balancing Performance and Manageability · IEEE Trans. Parallel Distributed Syst. 2014 |
Distributed systems
fault tolerance |
0.1 | 1 | 2012 | ReNIC: Architectural extension to SR-IOV I/O virtualization for efficient replication · ACM Trans. Archit. Code Optim. 2012 |
Cloud and datacenter computing › virtualization
i/o virtualization |
0.1 | 1 | 2012 | ReNIC: Architectural extension to SR-IOV I/O virtualization for efficient replication · ACM Trans. Archit. Code Optim. 2012 |
Distributed systems › replication
virtual machine replication |
0.1 | 1 | 2012 | ReNIC: Architectural extension to SR-IOV I/O virtualization for efficient replication · ACM Trans. Archit. Code Optim. 2012 |
Cloud and datacenter computing › datacenter services › online service systems › internet services
internet-scale services |
0.1 | 1 | 2009 | Design Patterns for Internet-Scale Services · ICDE 2009 |
Processor architecture and microarchitecture
latency hiding |
0.1 | 1 | 2007 | Latency hiding through multithreading on a network processor · PPoPP 2007 |
Processor architecture and microarchitecture
multithreading |
0.1 | 1 | 2007 | Latency hiding through multithreading on a network processor · PPoPP 2007 |
Cloud and datacenter computing › virtualization › virtual machine management
server consolidation |
0.1 | 1 | 2014 | HYVI: A HYbrid VIrtualization Solution Balancing Performance and Manageability · IEEE Trans. Parallel Distributed Syst. 2014 |
Cloud and datacenter computing › virtualization
virtual machine migration |
0.1 | 1 | 2014 | HYVI: A HYbrid VIrtualization Solution Balancing Performance and Manageability · IEEE Trans. Parallel Distributed Syst. 2014 |
Compilers and program optimization › parallelization
automatic parallelization |
0.1 | 1 | 2005 | Automatic multithreading and multiprocessing of C programs for IXP · PPoPP 2005 |
Concurrent programming › concurrency models
multithreading |
0.1 | 1 | 2005 | Automatic multithreading and multiprocessing of C programs for IXP · PPoPP 2005 |
Compilers and program optimization
parallelizing compiler |
0.1 | 1 | 2005 | Automatically partitioning packet processing applications for pipelined architectures · PLDI 2005 |
GPUs and heterogeneous computing › packet processing
packet processing pipelines |
0.1 | 1 | 2005 | Automatically partitioning packet processing applications for pipelined architectures · PLDI 2005 |
Parallel and multicore computing
pipeline parallelism |
0.1 | 1 | 2005 | Automatically partitioning packet processing applications for pipelined architectures · PLDI 2005 |
Cloud and datacenter computing
cloud infrastructure |
0.0 | 1 | 2012 | ReNIC: Architectural extension to SR-IOV I/O virtualization for efficient replication · ACM Trans. Archit. Code Optim. 2012 |
Distributed systems › distributed data processing
data partitioning and replication |
0.0 | 1 | 2009 | Design Patterns for Internet-Scale Services · ICDE 2009 |
Processor architecture and microarchitecture › special-purpose processor
network processor |
0.0 | 1 | 2007 | Latency hiding through multithreading on a network processor · PPoPP 2007 |
Internet architecture and protocols › packet processing
network processor |
0.0 | 1 | 2005 | Automatic multithreading and multiprocessing of C programs for IXP · PPoPP 2005 |
Internet architecture and protocols
packet processing |
0.0 | 1 | 2005 | Automatic multithreading and multiprocessing of C programs for IXP · PPoPP 2005 |
Methods — techniques the papers use, named apart from their topics
performance evaluation · 0.2paravirtualization · 0.2hardware acceleration · 0.2system simulation · 0.1checkpointing · 0.1program transformation · 0.1automatic synchronization insertion · 0.1design patterns · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | HYVI: A HYbrid VIrtualization Solution Balancing Performance and ManageabilityabstractVirtualization is a building block technology of cloud computing. Software virtualization solutions, such as paravirtualized Memory Management Unit and paravirtualized I/O, provide flexible manageability, such as virtual machine migration and IP-based network packet filtering. However, it suffers from performance and scalability issues. Hardware virtualization and its advanced accelerations, such as Extended Page Table and Single Root I/O Virtualization, were introduced later to simplify virtualization implementation and improve performance. However, this solution may suffer from a manageability issue. In this paper, we describe our work on the implementation of hardware virtualization and optimizations of the advanced hardware acceleration support in Xen to improve the virtualization performance and scalability. We further propose HYVI, a hybrid virtualization solution combining the advantages of software virtualization (manageability) and hardware virtualization (performance and scalability), to address performance and manageability issues. Finally, we present performance evaluations and characterizations of these hardware accelerations and hybrid virtualization, using both OS benchmarks and a server consolidation benchmark (vConsolidate). The results show that optimized hardware acceleration can achieve an up to 77 percent and 33 percent performance improvement over software full virtualization and paravirtualization in the server consolidation benchmark, respectively. Hybrid virtualization achieves an up to 1.56 × performance, with 0.69 lower CPU core usage of paravirtualization, and maintains flexible manageability. Yaozu Dong, Jinquan Dai, Haibing Guan |
IEEE Trans. Parallel Distributed Syst. | 3 |
| 2012 | ReNIC: Architectural extension to SR-IOV I/O virtualization for efficient replicationabstractVirtualization is gaining popularity in cloud computing and has become the key enabling technology in cloud infrastructure. By replicating the virtual server state to multiple independent platforms, virtualization improves the reliability and availability of cloud systems. Unfortunately, existing Virtual Machine (VM) replication solutions were designed only for software virtualized I/O, which suffers from large performance and scalability overheads. Although hardware-assisted I/O virtualization (such as SR-IOV) can achieve close to native performance and very good scalability, they cannot be properly replicated across different physical machines due to architectural limitations (such as lack of efficient device state read/write, buffering outbound packets, etc.). In this paper, we address those architectural limitations, by proposing ReNIC, an architectural extension to SR-IOV I/O virtualization for efficient I/O replications. We have extended Xen hypervisor and the Remus rapid checkpoint solution to support this new architectural extension. We developed a system simulator on multi-core systems to extensively evaluate ReNIC. The experimental results demonstrate that ReNIC achieves up to 54% CPU usage reduction, compared to software based I/O virtualization at runtime, and up to 16.2% performance advantage over software based I/O virtualization in rapid checkpoint. During migration, ReNIC reduces service shutdown time by about 50%, compared to device emulation and paravirtualized I/O, and over 71% compared to teaming driver. Yaozu Dong, Zhenhao Pan, Jinquan Dai, Yunhong Jiang |
ACM Trans. Archit. Code Optim. | 4 |
| 2011 | HiTune: Dataflow-Based Performance Analysis for Big Data Cloud
Jinquan Dai, Shengsheng Huang, Bo Huang 0002 |
USENIX ATC | 1 |
| 2009 | SharK: A Web 2.0 Service Infrastructure for Knowledge Sharing
Bo Huang 0002, Junyong Ding, Jinquan Dai |
CSEDU (1) | 3 |
| 2009 | Design Patterns for Internet-Scale ServicesabstractInternet-scale services need new design patterns and programming models for the partitioned data set with many copies that are changed independently. This is a huge software challenge. Big Web sites spend 70% of their efforts on undifferentiated heavy lifting (e.g., partitioning, replication and scaling) versus 30% on differentiated value (feature) creation. This talk will review the challenges for Internet-scale services and some of the emerging solutions to address those challenges, based on our experience in building Internet-scale service platforms as well as the industry best practices. Jinquan Dai |
ICDE | 1 |
| 2009 | Towards high-quality I/O virtualizationabstractHigh-quality I/O virtualization (that is, complete device semantics, full-feature set, close-to-native performance and real-time response) is critical to both server and client virtualizations. Existing solutions for I/O virtualization (e.g., full device emulation, paravirtualization and direct I/O) cannot meet the requirements of high-quality I/O virtualization due to high overheads, lack of complete semantic or full-feature set support. Yaozu Dong, Jinquan Dai, Zhiteng Huang, Haibing Guan, Kevin Tian, Yunhong Jiang |
SYSTOR | 2 |
| 2007 | Latency Hiding in Multi-Threading and Multi-Processing of Network Applications
Jinquan Dai, Zhiyuan Lv, Prashant R. Chandra |
PACT | 2 |
| 2007 | Pipelined Execution of Critical Sections Using Software-Controlled Caching in Network ProcessorsabstractTo keep up with the explosive Internet packet processing demands, modern network processors (NPs) employ a highly parallel, multi-threaded and multi-core architecture. In such a parallel paradigm, accesses to the shared variables in the external memory (and the associated memory latency) are contained in the critical sections, so that they can be executed atomically and sequentially by different threads in the network processor. In this paper, we present a novel program transformation that is used in the Intelreg Auto-partitioning C Compiler for IXP to exploit the inherent finer-grained parallelism of those critical sections, using the software-controlled caching mechanism available in the NPs. Consequently, those critical sections can be executed in a pipelined fashion by different threads, thereby effectively hiding the memory latency and improving the performance of network applications. Experimental results show that the proposed transformation provides impressive speedup (up-to 9.9times) and scalability (up-to 80 threads) of the performance for the real-world network application (a 10Gbps Ethernet Core/Metro Router) Jinquan Dai, Bo Huang 0002 |
CGO | 1 |
| 2007 | Latency hiding through multithreading on a network processorabstractNo abstract available. Jinquan Dai, Zhiyuan Lv, Prashant R. Chandra |
PPoPP | 2 |
| 2005 | Automatically partitioning packet processing applications for pipelined architecturesabstractModern network processors employs parallel processing engines (PEs) to keep up with explosive internet packet processing demands. Most network processors further allow processing engines to be organized in a pipelined fashion to enable higher processing throughput and flexibility. In this paper, we present a novel program transformation technique to exploit parallel and pipelined computing power of modern network processors. Our proposed method automatically partitions a sequential packet processing application into coordinated pipelined parallel subtasks which can be naturally mapped to contemporary high-performance network processors. Our transformation technique ensures that packet processing tasks are balanced among pipeline stages and that data transmission between pipeline stages is minimized. We have implemented the proposed transformation method in an auto-partitioning C compiler product for Intel Network Processors. Experimental results show that our method provides impressive speed up for the commonly used NPF IPv4 forwarding and IP forwarding benchmarks. For a 9-stage pipeline, our auto-partitioning C compiler obtained more than 4X speedup for the IPv4 forwarding PPS and the IP forwarding PPS (for both the IPv4 traffic and IPv6 traffic). Jinquan Dai, Bo Huang 0002, Luddy Harrison |
PLDI | 1 |
| 2005 | Automatic multithreading and multiprocessing of C programs for IXPabstractEffective compilation of packet processing applications onto the Intel IXP network processors requires, among other things, the automatic use of multiple threads on one or more processing elements, and the automatic introduction of synchronization as required to correctly enforce dependences between such threads. We describe the program transformation that is used in the Intel Auto-partitioning C Compiler for IXP to automatically multithread/multi-process a program for the IXP. This transformation consists of steps that introduce inter-thread signaling to enforce dependences, optimize the placement of such signaling, reduce the number of signals in use to the number available in hardware, and transform the initialization code for correct execution in the multithreaded version. Experimental results show that our method provides impressive speedup for six PPSes (Packet Processing Stages) in the widely used NPF IP forwarding benchmarks. For most packet processing stages, our algorithms can achieve almost linear performance improvement after automatic multi-threading transformation. The automatic multi-processing transformation help further boost the speedup of two PPSes. Bo Huang 0002, Jinquan Dai, Luddy Harrison |
PPoPP | 3 |
| 2004 | QROUTE: an QoS-guaranteed multicast routing
Jinquan Dai, Touchai Angchuan, Hung Keng Pung |
Comput. Commun. | 1 |
| 2002 | QROUTE: An Integrated Framework for QoS-Guaranteed MulticastabstractWe propose QROUTE, an integrated framework for QoS-guaranteed multicast, in which a feasible multicast tree meeting multiple QoS constraints can be constructed in a distributed fashion using local states at routers. The simplicity in the design and implementation of QROUTE has been demonstrated by prototyping a router testbed, whose measured performance is presented. Compared to other QoS-based multicast routing protocols, QROUTE is more effective because it searches all the available feasible paths in parallel so as to ensure a better chance of successful routing and a more efficient use of network resources. We also evaluate the performance of QROUTE by comparing it with other related protocols through simulations, and find that it has lower blocking probability, lower routing overhead and lower set-up latency; the resulting multicast trees of QROUTE also generally require fewer links than those of the related protocols. Jinquan Dai, Hung Keng Pung, Touchai Angchuan |
LCN | 1 |