Physical layout techniques of automatic placement and interconnection routing are discussed. The placement section begins with a description of alternate technologies (gate array versus standard cell), followed by a discussion of various techniques and metrics used in placement algorithms. Two standard cell placement algorithms are briefly discussed. Next, a model of placement difficulty is developed in order to gain some insight into modern layout problems. The mathematical property of convexity and its importance to the placement problem is developed. The use of a convex quadratic objective function as a practical layout metric is discussed in some depth. Conventional routing sequences and algorithms are described in moderate detail. Some newer techniques are also discussed. Finally, special case routing problems and approaches are briefly described.

One of the methods of increasing routability of an integrated circuit or printed circuit board, is to improve the assignment of connection nets to component (gate, chip, etc.) pins. The quality of a pin assignment is judged based on factors such as predicted wire length, wiring crossovers, and wiring congestion. This paper describes topological heuristic algorithms for pin assignment. Two stages, initial pin assignment and assignment improvement, are described in detail. For all cases, example diagrams are provided. The heuristic approaches demonstrated are highly tunable to specific routers.