The influence of adaptive baseband equalization on decision-feedback carrier recovery performance is investigated. First, it is shown that the delay introduced by the equalizer in the carrier recovery loop does not have basic consequences on system performance. Second, the interaction between the two adaptive circuits is studied for four different equalizer adaptation algorithms. It is found that algorithms based on the zero-forcing criterion are unstable unless they are used with an appropriate constraint. With gradient-type algorithms based on the minimum mean square error criterion, the interaction leads to an improved carrier acquisition performance at the expense of a larger phase jitter. It is therefore concluded that even with these latter algorithms it is generally worthwhile to avoid the interaction by forcing the imaginary part of the equalizer reference tap to zero. The theoretical analysis (carried out with a single complex tap equalizer) is supported by experimental results and computer simulation.

Two algorithms are presented for optimum timing recovery in digitally implemented equalizers. The first one is a polarity-type algorithm based on the conventional minimum mean-square error criterion. A theoretical analysis is made to characterize the algorithm phase detector and evaluate its steady-state phase jitter variance. Influence of various channel and system design parameters on the algorithm performance is illustrated using phase jitter probability densities obtained by means of computer simulations. Interaction of the algorithm with decision-directed carrier recovery is also examined. It is shown that interaction with carrier recovery may considerably degrade the timing acquisition performance, and a second algorithm is then presented which eliminates this interaction. The second algorithm is based on the minimization of a modified mean-square error criterion which provides a measure of the intersymbol interference, independently of the carrier phase. Decision-directed timing and carrier recoveries are thus decoupled and the system startup period is considerably reduced. Phase detector characteristic and steady-state jitter performance of the second algorithm are evaluated by analytical means and computer simulations, as in the first algorithm.