This paper proposes a dual loop low-dropout regulator (LDO) for heavy load current (I$_{\mathbf {L}}$). The proposed LDO features a fast load transient response and wide output capacitor (C$_{\mathbf {O}}$) range. The proposed dynamic negative feedback loop (DNFL) enhances the transient response by reducing the undershoot and widening the bandwidth. The transient response is improved further by the proposed dynamic G$_{\mathbf {m}}$boosting error amplifier. The C$_{\mathbf {O}}$range gets wider thanks to the proposed DNFL, which introduces an additional zero in the feedback loop. The zero secures stability in a wide C$_{\mathbf {O}}$range. The prototype of the proposed LDO is fabricated in a 0.5-$\mu $m CMOS process. The input voltage (V$_{\mathbf {IN}}$) ranges from 2.7 to 4.2 V, while the output voltage (V$_{\mathbf {O}}$) ranges from 2.4 to 4.0 V. The maximum I$_{\mathbf {L}}$is 2 A. The prototype provides enough phase margin across a C$_{\mathbf {O}}$range from 0 to$1~\mu $F. The measured results show a 68-mV undershoot with a load current of 2.5 A/$1~\mu $s on a 0-$\mu $F C$_{\mathbf {O}}$capacitor. When the C$_{\mathbf {O}}$is$1~\mu $F under the same conditions, the proposed LDO features an undershoot of 13 mV. The proposed LDO achieves the best FoM among the state-of-the-art LDOs without and with the off-chip C$_{\mathbf {O}}$. In cases where the off-chip C$_{\mathbf {O}}$is not employed, the achieved FoM is 5.228 ps$\cdot V/\mu $m2. When using the off-chip C$_{\mathbf {O}}$, the FoM is 0.624 ps/$\mu $m2.

The dichromatic reflection model has been popularly exploited for computer vison tasks, such as color constancy and highlight removal. However, dichromatic model estimation is an severely ill-posed problem. Thus, several assumptions have been commonly made to estimate the dichromatic model, such as white-light (highlight removal) and the existence of highlight regions (color constancy). In this paper, we propose a spatio-temporal deep network to estimate the dichromatic parameters under AC light sources. The minute illumination variations can be captured with high-speed camera. The proposed network is composed of two sub-network branches. From high-speed video frames, each branch generates chromaticity and coefficient matrices, which correspond to the dichromatic image model. These two separate branches are jointly learned by spatio-temporal regularization. As far as we know, this is the first work that aims to estimate all dichromatic parameters in computer vision. To validate the model estimation accuracy, it is applied to color constancy and highlight removal. Both experimental results show that the dichromatic model can be estimated accurately via the proposed deep network.

Most of the lights surrounding our world are artificial lights, whose power is supplied by alternative current (AC). The intensities of these lights are dynamically varying with time. In this paper, we propose a novel deep-learning based method for temporal color constancy. We capture this intensity variation of AC lights using high-speed camera, and use it as a close cue to learn an illuminant chromaticity. While most of the existing methods estimate an illuminant from spatial pixels, the proposed method learns temporal feature via AC flickers of a high-speed video. To effectively learn a temporal feature, the high-speed temporal correlation is fed into the proposed network, and helps it to concentrate on illuminant-attentive regions. As a result, the proposed method works well under complex illuminant environment with ambient lights, which was a very hard problem for existing spatial methods. Experimental results show that the proposed method outperforms all existing methods, and demonstrate that it works very robustly under various illuminant environments.

This paper presents a Via programmable read only memory (Via-ROM) for Vminand macro-yield enhancement through robust ROM designs based on 45nm process. The main stability issues in ROM are 1) lower on-cell (NMOS) current, 2) higher keeper (PMOS) current, and 3) higher bit-line (BL) parasitic value. To improve the Vminand macro-yield, the robust ROM design schemes are implemented as follows. 1) ROM bit cell size optimization without increasing a bit cell area, 2) BL loading reduction to use a rom code pattern optimization, 3) selective full BL pre-charge and keeper control to use an external pin named as KCS (Keeper Control Signal) and 4) wide pulse width generator using an asynchronous 3-bit ripple binary counter. These schemes to improve 0 read margin were confirmed by both the simulation and the measurement. Experimental results show that macro-yield improved from 0% to 100% at 1.1V (Voperation) and -40°C.

This paper presents a novel silicon controlled rectifier (SCR)-based (Electrostatic Discharge) ESD protection devices for I/O clamp and power clamp. The proposed ESD protection devices has a high holding voltage and a low tigger voltage characteristic than conventional SCR. These characteristics enable to latch-up immune under normal operating conditions as well as superior full chip ESD protection. Also, the proposed devices can provide area efficiency in comparison to conventional (Gate Grounded NMOS) GGNMOS. The proposed devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) technology. From the experimental results, the device for Input/Output (I/O) clamp has a trigger voltage of 6.5V, 7.7V and 8.1V with the LG1 of 0.5um, 0.8um and 1um, respectively. And the device for power clamp has a holding voltage of 8V 10V and 11.3V with the D1 of 4.5um, 5.5um and 7um. Also, the device for I/O clamp has trigger voltage of 7.8V to 8.9V with the gate length (LG1) of 0.5um, 0.8um and 1.0um. Moreover, The proposed devices have high ESD robustness.