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B. I. Strom

dblp:86/1396 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1979
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design		 0.011979
Proof of the Equivalent Realizability of a Time-Bound Arbiter and a Runt-Free Inertail Delay · ISCA 1979
Integrated circuit design › digital circuit design
inertial delay element		 0.011979
Proof of the Equivalent Realizability of a Time-Bound Arbiter and a Runt-Free Inertail Delay · ISCA 1979
YearPublicationVenuePosition
1979 Proof of the Equivalent Realizability of a Time-Bound Arbiter and a Runt-Free Inertail Delay
abstract
This paper proves that, given a reliable time-bounded arbiter, it is possible to realize a reliable (i.e. runt-free) inertial delay, and vice-versa. It therefore shows that the time-bounded arbiter and the inertial delay are equally realizable. Consequently all theoretical limitations which apply to one will apply, in some form, to the other as well.
B. I. Strom
 ISCA1