A methodology for automated synthesis of mixed analog/digital hardware architectures for Artificial Neural Network (ANN) applications is presented, The ANN system is input in the form of a Data Flow Graph (DFG) of operators. The output is a high-level interconnection description of mixed analog/digital building block circuits that is generated by searching a multidimensional design space to satisfy the throughput requirements and minimize an area-time cost function. A combination of quantitative analysis and behavioral modeling techniques tackles the problems of hardware nonidealities by screening suitable analog circuits. Digital hardware is employed when no analog circuit is found that satisfies the performance requirements of any operation. A heuristic partitioning scheme reduces the interfaces between blocks of circuits operating in analog and digital modes. The parallelism in ANN systems is, handled by a new scheduling and allocating procedure that selectively sequentializes groups of operations with the goal of iteratively improving an area-time cost function. The synthesizer is also capable of embedding hardware units that are intended to operate asynchronously. The synthesis methodology is illustrated with two design examples.>