SPICE based circuit simulation is a traditional workhorse in the VLSI design process. Given the pivotal role of SPICE in the IC design flow, there has been significant interest in accelerating SPICE. Since a large fraction (on average 75%) of the SPICE runtime is spent in evaluating transistor model equations, a significant speedup can be availed if these evaluations are accelerated. This paper reports on our early efforts to accelerate transistor model evaluations using a Graphics Processing Unit (GPU). We have integrated this accelerator with a commercial fast SPICE tool. Our experiments demonstrate that significant speedups (2.36times on average) can be obtained. The asymptotic speedup that can be obtained is about 4times. We demonstrate that with circuits consisting of as few as about 1000 transistors, speedups in the neighborhood of this asymptotic value can be obtained. By utilizing the recently announced (but not currently available) quad GPU systems, this speedup could be enhanced further, especially for larger designs.

Advances in GPU technology have propelled the GPU into arenas far afield from the traditional, isolated roles they have previously played. With hundreds of processing units in a single GPU, substantial speedups can be achieved by harnessing their power to augment the performance of the traditional single- or multi-core CPU on certain compute-intensive applications. However, utilizing the GPU requires both a change in the programmer's traditional algorithmic model as well as a judicious selection of algorithm being used for the problem. This paper reviews the GPU architecture and the tools available to utilize this valuable resource. It also provides insight into the type of problem best suited for the GPU as well as programming styles required to fully harness the power of the GPU. We present examples of specific EDA algorithms that can benefit from GPU acceleration, using both the CUDA and OpenCL environments.

The design of complex mixed-signal system-on-a-chip (SOC) designer poses challenging requirements on the simulation design environment. The simulation platform has to include simulations at the behavioral, gate and transistor-level which have traditionally been done in separate environments. As the scaling trend continues, the designer needs additional accuracy and capacity, new capabilities such as efficient statistical simulation that takes into account layout dependent effects. In this panel we have representatives from the CAD and design community discussing the challenges and current solutions available to the mixed-signal simulation challenge.

In order to adequately account for nanometer effects during timing analysis, archaic standard cell models must be replaced. Simplifying assumptions used during characterization, such as nearly linear voltage inputs or lumped-capacitance loads, are no longer valid. Signal integrity analysis further complicates the characterization process because the typical voltage waveform used during characterization does not contain a noise component. This paper introduces two new technologies for standard cell and interconnect timing analysis: Blade and Razor. Blade is a novel cell model and runtime engine based on current flow. Razor is the accompanying interconnect model. Both Blade and Razor produce and consume arbitrary voltage waveforms with near-SPICE accuracy at speeds tens of thousands of times faster than SPICE.

Cell characterization data is used by synthesis and timing verificationtools to compile and validate a cell netlist which meets timingconstraints imposed by the designer. Characterization tablescontain data for multiple, simple equations representing a cell's behaviorand are an alternative to the single, monolithic characteristicequation. Data in the table is fit to a function whose form isfixed by the application, and the cellýs response is interpolated fromthe function. Tables can potentially increase accuracy, but large tablescan cause a program to use dramatically more memory and runmuch slower. The optimization of characterization tables, in whichaccuracy is maintained but table size is significantly reduced, is importantif large programs, such as synthesis, are to complete accuratelyand in a reasonable runtime. In this paper we address someof the issues involved in characterizing cells and optimizing characterizationtables quickly and accurately. Experimental results fromthe use of these techniques within AMD for a Synopsys cell libraryis also presented.