Demo Data from SIGIR 2026 / reviewers in the wild / expert
Robert Cooksey
dblp:86/6374
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2002
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.0 | 1 | 2002 | A stateless, content-directed data prefetching mechanism · ASPLOS 2002 |
Memory systems › cache › prefetching
data prefetching |
0.0 | 1 | 2002 | A stateless, content-directed data prefetching mechanism · ASPLOS 2002 |
Memory systems
memory access latency |
0.0 | 1 | 2002 | A stateless, content-directed data prefetching mechanism · ASPLOS 2002 |
Operating systems › resource management › memory management
memory allocation |
0.0 | 1 | 2002 | A stateless, content-directed data prefetching mechanism · ASPLOS 2002 |
Methods — techniques the papers use, named apart from their topics
content-directed prefetching · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2002 | A stateless, content-directed data prefetching mechanismabstractAlthough central processor speeds continues to improve, improvements in overall system performance are increasingly hampered by memory latency, especially for pointer-intensive applications. To counter this loss of performance, numerous data and instruction prefetch mechanisms have been proposed. Recently, several proposals have posited a memory-side prefetcher; typically, these prefetchers involve a distinct processor that executes a program slice that would effectively prefetch data needed by the primary program. Alternative designs embody large state tables that learn the miss reference behavior of the processor and attempt to prefetch likely misses.This paper proposes Content-Directed Data Prefetching, a data prefetching architecture that exploits the memory allocation used by operating systems and runtime systems to improve the performance of pointer-intensive applications constructed using modern language systems. This technique is modeled after conservative garbage collection, and prefetches "likely" virtual addresses observed in memory references. This prefetching mechanism uses the underlying data of the application, and provides an 11.3% speedup using no additional processor state. By adding less than ½% space overhead to the second level cache, performance can be further increased to 12.6% across a range of "real world" applications. Robert Cooksey, Stéphan Jourdan, Dirk Grunwald |
ASPLOS | 1 |