In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. Neuromorphic systems realize the function of biological neural systems by emulating their structure. Designers of such systems face three major design choices: 1) whether to emulate the four neural elements-axonal arbor, synapse, dendritic tree, and soma-with dedicated or shared electronic circuits; 2) whether to implement these electronic circuits in an analog or digital manner; and 3) whether to interconnect arrays of these silicon neurons with a mesh or a tree network. The choices we made were: 1) we emulated all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; 2) we realized all electronic circuits except those for axonal arbors in an analog manner; this choice maximized energy efficiency; and 3) we interconnected neural arrays in a tree network; this choice maximized throughput. These three choices made it possible to simulate a million neurons with billions of synaptic connections in real time-for the first time-using 16 Neurocores integrated on a board that consumes three watts.

We present a 1-change-in-4 (1c4) link for interchip communication that extends level-encoded dual-rail (LEDR). LEDR transmits a bit on every transition by using all four 2bit codewords, with the bit encoded by the current codeword (level-encoding) rather than the difference between it and the previous codeword (transition signaling). 1c4 transmits two bits on every transition by using all sixteen 4-bit codewords, preserving LEDR's level-encoding property. Delay-insensitive I/O pad implementations for 1c4 encoding and decoding are described. Measurements of this chip-to-chip link, fabricated in a 0.18μm CMOS process, yielded a peak data-rate of 315 Mb/s at 1.8V and an energy efficiency of 89.8pJ/bit.