Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from SIGIR 2026 / reviewers in the wild / expert

H. Levy

dblp:88/3822 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Integrated circuit design · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › interconnect modeling
interconnect parasitic modeling		 0.012000
A rank-one update method for efficient processing of interconnect parasitics in timing analysis · DAC 2000
Electronic design automation
timing analysis		 0.012000
A rank-one update method for efficient processing of interconnect parasitics in timing analysis · DAC 2000
Integrated circuit design › interconnect
interconnect parasitics		 0.012000
A rank-one update method for efficient processing of interconnect parasitics in timing analysis · DAC 2000

Methods — techniques the papers use, named apart from their topics

rank-one update · 0.0model order reduction · 0.0
YearPublicationVenuePosition
2000 A rank-one update method for efficient processing of interconnect parasitics in timing analysis
abstract
In this paper we presen t a rank-one update method for updating reduced-order models of interconnect parasitics when driv e resistances or load capacitances change, as commonly occurs during timing analysis. These rank-one updates are extremely inexpensive, do not require reexamining the original in terconnect netw ork, and most importantly are provably equivalent to rereducing the original netw ork. This abstract con tains the proof only for the case of varying the driver resistance, but examples are given to show that the exactness holds more generally. In particular, a cross-talk case is examined where the conductance matrix is singular.
H. Levy, W. Scott, Don MacMillen, Jacob K. White 0001
 DAC1