This paper presents a study of DDR4 DRAM faults in a large fleet of commodity servers, covering several billion memory device-hours of data. The goal of this study is to understand faults in DDR4 DRAM devices to measure the efficacy of existing hardware resilience techniques and aid in designing more resilient systems for future large-scale systems.The study has several key findings about the fault characteristics of DDR4 DRAMs and adds several novel insights about system reliability to the existing literature. Specifically, the data show sixteen unique fault modes in the DDR4 DRAM under study, including several that have not been previously reported. Over 45% of the faults that occurred affected multiple DRAM bits. The time-to-failure characteristics of faults internal to the DRAM die differ from those external to the DRAM die. We also examine faults from multiple DRAM vendors, finding that fault rates vary by more than 1.34x among vendors.Finally, we use the data to compare chipkill ECC and an ECC that covers a DDR5 "bounded fault." Given the fault rates in this data, a bounded fault ECC increases the rate of faults that cause uncorrectable errors by up to 5.71 FIT per DRAM device compared to chipkill ECC.

The pace of advancement of the top-end supercomputers historically followed an exponential curve similar to (and driven in part by) Moore's Law. Shortly after hitting the petaflop mark, the community started looking ahead to the next milestone: Exascale. However, many obstacles were already looming on the horizon, such as the slowing of Moore's Law, and others like the end of Dennard Scaling had already arrived. Anticipating significant challenges for the overall high-performance computing (HPC) community to achieve the next 1000x improvement, the U.S. Department of Energy (DOE) launched the Exascale Computing Program to enable and accelerate fundamental research across the many technologies needed to achieve exascale computing.

In this paper, we introduce DeepSwapper, a deep learning-based page swap management scheme that utilizes RNN to perform fast, energy-efficient, and temperature-aware page swapping in hybrid memory systems. DeepSwapper comprises of LSTM units of RNN model to predict the future memory accesses to guide its swap management scheme, a dynamic page swap management scheme that utilizes DRAM capacity efficiently by enabling hot pages in a swap group to be swapped with cold pages of another swap group, and a temperature-aware page swap management scheme, which first predicts the future writes to NVM pages and then, decides to migrate those pages with frequent writes in hot NVM banks to DRAM to enhance the NVM lifetime.

With the increase in the number of data-intensive applications on today's workloads, DRAM-based main memories are struggling to satisfy the growing data demand capacity. Phase Change Memory (PCM) is a type of non-volatile memory technology that has been explored as a promising alternative for DRAM-based main memories due to its better scalability and lower leakage energy. Despite its many advantages, PCM also has shortcomings such as long write latency, high write energy consumption, and limited write endurance, which are all related to the write operations. In this article, we propose a novel writeback-aware Last Level Cache (LLC) management scheme named WALL to reduce the number of LLC writebacks and consequently improve performance, energy efficiency, and lifetime of a PCM-based main memory system. First, we investigate the writeback behavior of LLC sets and show that writebacks are not uniformly distributed among sets; some sets observe much higher writeback rates than others. We then propose a writeback-aware set-balancing mechanism, which employs the underutilized LLC sets with few writebacks as an auxiliary storage for the evicted dirty lines from sets with frequent writebacks. We also propose a simple and effective writeback-aware replacement policy to avoid the eviction of the dirty blocks that are highly reused after being evicted from the cache. Our experimental results show that WALL achieves an average of 30.9% reduction in the total number of LLC writebacks, compared to the baseline scheme, which uses the LRU replacement policy. As a result, WALL can reduce the memory energy consumption by 23.1% and enhance PCM lifetime by 1.29×, on average, on an 8-core system with a 4GB PCM main memory, running memory-intensive applications.

ReRAM-based systems are attractive implementation alternatives for neuromorphic computing because of their high speed and low design cost. In this work, we investigate the impact of temperature on the ReRAM-based neuromorphic architectures and show how varying temperatures have a negative impact on the computation accuracy. We first classify ReRAM crossbar cells based on their temperature and identify effective neural network weights that have large impacts on network outputs. Then, we propose a novel temperature-aware training and mapping scheme to prevent the effective weights from being mapped to hot cells to restore the system accuracy. Evaluation results for a two-layer neural network show that our scheme can improve the system accuracy by up to 39.2%.

In this paper, we propose WALL, a novel writeback-aware LLC management scheme to reduce the number of LLC writebacks and consequently improve performance, energy efficiency, and lifetime of a PCM-based main memory system. First, we investigate the writeback behavior of LLC sets and show that writebacks are not uniformly distributed among sets; some sets observe much higher writeback rates than others. We then propose a writeback-aware set-balancing mechanism, which employs the underutilized LLC sets with few writebacks as an auxiliary storage for storing the evicted dirty lines of sets with frequent writebacks. We also propose a simple and effective writeback-aware replacement policy to avoid the eviction of the writeback blocks that are highly reused after being evicted from the cache. Our experimental results show that WALL achieves an average of 26.6% reduction in the total number of LLC writebacks, compared to the baseline scheme, which uses the LRU replacement policy. As a result, WALL can reduce the memory energy consumption by 19.2% and enhance PCM lifetime by 1.25x, on average, on an 8-core system with a 4GB PCM main memory, running memory intensive applications.

Resistive RAM (ReRAM) is an emerging memory technology that has been proposed as a promising alternative for DRAM-based main memory. In addition to being more scalable and non-volatile, ReRAM also has the capability of performing logic functions. In this paper, we aim to investigate using 3D stacked ReRAM to achieve a scalable and high-performance memory system architecture. 3D integration of ReRAM crossbar layers (i.e., 3D crossbar) is a potential method for further improving ReRAM density. However, 3D architectures typically suffer from high operating temperatures, which adversely impact ReRAM reliability and device performance. The objective of this study is to address ReRAM endurance limitations, which is a major drawback for such resistive memory technologies. Specifically, we analyze the impact of temperature on ReRAM endurance in 3D and 2.5D stacking designs and show that stacking ReRAM onto multicore dies (i.e., 3D stacking design) may cause lifetime concerns. We then propose a novel solution to improve the access efficiency and reduce the number of accesses to the overheated ReRAM banks. The goal of our mechanism which is mainly utilized for the 2.5D design, is to perform slower and fewer accesses to hot banks to cool them. Evaluation results show that our technique called THOR, can achieve 2.06× lifetime enhancement and 7.5°C peak temperature reduction over a baseline design with only 1.9% performance degradation while running on the 2.5D design.

In this work, we develop a 3D architecture that utilizes STT-RAM for the last level cache (LLC). 3D integration enables large LLCs to be stacked onto a die. However, 3D architectures suffer from higher operating temperatures due to increased power densities. The elevated temperatures can adversely impact the STT-RAM performance and reliability. The objective of this paper is to address the limits of integrating STT-RAM in 3D chip stacks from a thermal perspective and propose a novel stacking structure that minimizes heat-induced problems. Specifically, we analyze the system-level impact of increased temperatures and propose a novel technique to dynamically adjust the flow rate of the liquid interlayer cooling at run time to reduce the STT-RAM temperature and alleviate temperature-induced problems that cause the performance degradation and prevent overcooling the STT-RAM die and minimize the pump energy consumption. Evaluation results reveal that our approach achieves up to 19.1% performance improvement and 14.6% power reduction over an architecture that does not include an insulating layer.

In this paper, we introduce Therma, a thermal-aware run-time thread migration mechanism for managing temperature fluctuations in nanophotonic networks. Nanophotonics is one of the most promising communication substrate candidates for next-generation high-performance systems. However, their underlying components are sensitive to temperature fluctuations. These fluctuations arise mostly because of the temperature changes on the cores, which are adjacent to nanophotonic components. Therma minimizes thermal fluctuations on these temperature sensitive components by moving threads across cores. Evaluation results reveal that when each core is executing a single thread, Therma achieves a 15.4% and 6.1% reduction in the photonic power consumption compared to the baseline and an interconnectoblivious thread migration scheme, respectively. It also reduces photonic power consumption by up to 20.7% compared to the alternatives when running multiple threads per core on the system.

In this paper, we introduce MIN, a novel method for assigning wavelengths to nodes dynamically on a nanophotonic network to minimize the impact of process variations (PVs). Among the available wavelengths on a waveguide, a subset of them, called bubbles, are left intentionally unused. These bubbles are then borrowed by nodes dynamically to improve the channel utilization. We present an express wavelength regulation approach to manage these assignments efficiently. Evaluation results reveal that MIN can recover 80% of bandwidth loss due to PVs and achieve 41% trimming power reduction compared to state-of-the-art alternative approaches.

This paper presents a novel methodology to provide a promising solution for complex on-chip communication problems in order to reduce power consumption and delay. Our proposed reconfigurable Network-on-Chip (NoC) architecture is integrated with the radio frequency Interconnect (RF-I) with signal propagation at the speed of light. It is based on setting up express shortcut paths (ESPs) which include single-cycle multi-hop RF-I shortcut between selected pairs of NoCs cores. Hence, the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these ESPs. In this scheme, ESPs are constructed based on an energy model and performance constraints to accelerate critical communication path at the design time. Further, we also try to optimize these ESPs by using a novel flow control at a run time. Additionally, a suitable routing algorithm is suggested to support the packet to reach their destinations appropriately without struggling in congested paths. The experimental results captured by SoCs applications reveal that in comparison with the conventional NoC router, the proposed router takes 49% and 74% reduction in latency and energy, respectively besides 8.7% area overhead.