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Pierre Guebels

dblp:89/4513 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
hardware verification
0.011989
Rule-based VLSI Verification System Constrained by Layout Parasitics · DAC 1989
Electronic design automation
layout parasitics
0.011989
Rule-based VLSI Verification System Constrained by Layout Parasitics · DAC 1989
Electronic design automation › physical design
parasitic extraction
0.011989
Rule-based VLSI Verification System Constrained by Layout Parasitics · DAC 1989

Methods — techniques the papers use, named apart from their topics

formal verification · 0.0
YearPublicationVenuePosition
1989 Rule-based VLSI Verification System Constrained by Layout Parasitics
abstract
This paper addresses a rule-based method for VLSI design review, constrained by parasitics. Using the new ideas discussed in this paper, extraction from layout is not limited anymore to conventional electrical data, but additionally allows modelling of functional and timing behaviour. An extendable rule based validation algorithm operates on extracted models, decorated with parasitic effects, to formally prove most aspects of design correctness.
Jacques Wenin, Johan Verhasselt, Marc Van Camp, Jean Leonard, Pierre Guebels
DAC5