Recording and annotating real sound events for a sound event localization and detection (SELD) task is time consuming, and data augmentation techniques are often favored when the amount of data is limited. However, how to augment the spatial information in a dataset, including unlabeled directional interference events, remains an open research question. Furthermore, directional interference events make it difficult to accurately extract spatial characteristics from target sound events. To address this problem, we propose an impulse response simulation framework (IRS) that augments spatial characteristics using simulated room impulse responses (RIR). RIRs corresponding to a microphone array assumed to be placed in various rooms are accurately simulated, and the source signals of the target sound events are extracted from a mixture. The simulated RIRs are then convolved with the extracted source signals to obtain an augmented multi-channel training dataset. Evaluation results obtained using the TAU-NIGENS Spatial Sound Events 2021 dataset show that the IRS contributes to improving the overall SELD performance. Additionally, we conducted an ablation study to discuss the contribution and need for each component within the IRS.

Recent advancements of spatial audio technologies to enhance human’s emotional and immersive experiences are gathering attention. Many studies are clarifying the neural mechanisms of acoustic spatial perception; however, they are limited to the evaluation of mechanisms using basic sound stimuli. Therefore, it remains challenging to evaluate the experience of actual music contents and to verify the effects of higher-order neurophysiological responses including a sense of immersive and realistic experience. To investigate the effects of spatial audio experience, we verified the psychophysiological responses of immersive spatial audio experience using sound field synthesis (SFS) technology. Specifically, we evaluated alpha power as the central nervous system activity, heart rate/heart rate variability and skin conductance as the autonomic nervous system activity during an acoustic experience of an actual music content by comparing stereo and SFS conditions. As a result, statistically significant differences (p < 0.05) were detected in the changes in alpha wave power, high frequency wave power of heart rate variability (HF), and skin conductance level (SCL) among the conditions. The results of the SFS condition showed enhanced the changes in alpha power in the frontal and parietal regions, suggesting enhancement of emotional experience. The results of the SFS condition also suggested that close objects are grouped and perceived on the basis of the spatial proximity of sounds in the presence of multiple sound sources. It is demonstrating that the potential use of SFS technology can enhance emotional and immersive experiences by spatial acoustic expression.

TOSHIBA has developed a mobile application processor for multimedia mobile applications in 40 nm with a H.264 full high-definition (full-HD) video engine and a video/audio multiprocessor for various CODECs and image processing. The application processor has 25 power domains to achieve coarse-grain power gating for adjusting to the required performance of wide range of multimedia applications. Furthermore, the application processor has Stacked Chip SoC (SCS) DRAM I/F to achieve high memory bandwidth with low power consumption.

In this paper, we propose a remote measurement system of surface compliance distributions for haptic broadcasting. Our system is composed of an ultrasound phased array generating acoustic radiation pressure on the remote object surface and a laser displacement sensor. The compliance is evaluated by the ratio of the surface displacement to the applied force. We set up a system to examine the feasibility of the method. In the experiments, the distribution of the surface compliance comparable to the human skin was successfully measured for a flat object surface.

A single-chip MPEG-4 audiovisual LSI based on the proposed scalable multiprocessor architecture has been developed for IMT-2000 multimedia applications. The LSI consists of three 16-bit multimedia-extended RISC processors and dedicated hardware accelerators, so as to achieve both low power consumption and high cost-effectiveness. It handles the MPEG- 4 video SP@L1 codec with the QCIF image at 15 frames per second, the AMR speech codec, and the ITU-T H.223 multiplexing at 60MHz consuming only 80mW, which is 33% of the previous design. The MPEG-4 audiovisual LSI was fabricated in 0.18us CMOS technology with quad metal using the embedded DRAM.

A scalable MPEG-4 video codec architecture is proposed to achieve low power consumption and high cost-effectiveness for IMT-2000 multimedia applications. The MPEG-4 video codec consists of a 16-bit multimedia-extended RISC processor and dedicated hardware accelerators, which bring about both low power consumption and programmability. The proposed architecture is extended and applied for the development of two MPEG-4 LSIs. One is an MPEG-4 video codec LSI, which performs an MPEG-4 video encoding and decoding at 15 frames per second with quarter common intermediate format. The other is an MPEG-4 audiovisual LSI, containing three 16-bit RISC processors and a 16-Mbit embedded DRAM, executes the major functions of 3GPP 3G-324M video telephony for IMT-2000 applications. By introducing the optimization of the embedded DRAM configuration, clock gating technique, and low power motion estimation, the MPEG-4 audiovisual LSI consumes only 240 mW when it activates MPEG-4 video SP@L1 codec, the AMR speech codec, and the H.223 annex B multiplex at 60 MHz clock rate.

This paper describes a fully automated low-power design methodology in which three different voltage-scaling techniques are combined together. Supply voltage is scaled globally, selectively, and adaptively while keeping the performance. This methodology enabled us to design an MPEG4 codec core with 58% less power than the original in three week turn-around-time.

A new cache coherence solution is proposed for an over 500 MHz on-chip multiprocessor using advanced VLSI technology. In order to reduce shared-bus transaction time, the central coherence unit (CCU) is introduced. The CCU controls all shared-bus transactions, monitoring all cache rays every clock cycle, and executes a bus transaction in four clock cycles while a conventional bus mechanism requires eight clock cycles. A new cache coherence protocol (CRAC) is also introduced in order to reduce external memory access. The CRAC protocol makes it possible to load a desired data from any cache having a copy, and to transfer write-back responsibility to another cache having a copy. An implementation of CCU and CRAC is presented and evaluated using a cycle-based multiprocessor simulator. Simulation results show that introduction of CCU and CRAC is effective to reduce shared-bus traffic and total execution time. Furthermore, proposed multiprocessor model with CCU and CRAC is proved to be more scalable than a conventional multiprocessor model.

Two peripheral processor LSIs, the FTI (fast timed input port) and the FTO (fast timed output port), have been developed for real-time pulse handling. By using the time-wheel scheme, these processors provide a high-level command interface with the host CPU, thus alleviating the CPU load. New features, such as time difference measurement between channels and user reprogrammability during operation have been realized using this approach. The prototypes of both FTI and FTO were designed and fabricated using a 1.5- mu m CMOS sea-of-gates technology, and demonstrated the effectiveness of the time-wheel scheme.>