Recent impressive growth of AI applications in the most diversified heterogeneous domains is largely motivated by the availability of hardware accelerators used from the backstage of data centers (such as TPU, Tensor Processing Units, or VPUs, Visual Processing Units) to the far edge of embedded devices equipped with DPUs and Deep Learning Processing Units. High level toolchains for a more friendly usability of these platform had similar relevance in the process. In this paper we considered edge devices that provide an essential contribution for the deployment of “distributed intelligence” and are used typically at the gateway, CPE or Edge computing level. One of the typical assumptions is that Field Programmable Gate Array (FPGA) are far more expensive - with respect to power consumption - than legacy SBCs (single board computers). The main contribution of the paper is a fair comparison (at the same clock frequency and with the same main CPU) of processing time and power consumption of two different boards used for deep neural network classification. We will highlight the relevance of classification speed with respect to common KPIs adopted to compare the performances of automatic classification such as Loss, Precision, Recall, etc. This will be particularly relevant in the challenging domains of hardware accelerated real time control loops to provide distributed intelligence at the application level but also at the inner functions of emerging networking architectures.

This paper is concerned with an algorithm for Boolean factoring. In an earlier paper [1993], the author proposed a new algorithm for Boolean factoring that does not require any minimization step. The technique used for generating Boolean products rests on the notion of elementary rectangle. In this paper, we present two substantial improvements to this algorithm. The first is a new factoring strategy. The second is a new expansion technique. The modified algorithm outperforms the original one both in efficiency and quality of results.>

An algorithm for algebraic factorization of single-output functions is presented. The algorithm is based on the generation of some products covering a set of true cubes suitably chosen. The products forming a near-optimal factored expression are locally chosen from the ones covering each of those cubes. In order to obtain a good factorization, heuristics are used in the three procedures of which the method is composed. The algorithm is compared to a QUICK-FACTOR-like algorithm, using a large set of randomly generated functions. and it provides good results.>

The minimization algorithms which do not require any preliminary generation of all the prime implicants (PI's) of a function are the most efficient. In this work a new algorithm is described which follows such an approach. It is based on a local selection of PI's carried out by examining a set of vertices whose number is never greater than the number of PI's of a minimum cost cover. This algorithm takes advantage of a technique which uses numerical equivalents of the function vertices as pointers. For this reason it is well suited for implementation by computer. To illustrate the features of this algorithm a few examples are reported.