This paper presents an accurate dB-linear programmable-gain amplifier with temperature-robust characteristic. A novel Gm-cell feedback topology is proposed to provide linear gain control as well as bandwidth extension without any extra power consumption. Moreover, a PTAT bias is employed to further promote the temperature robustness while AC coupling stages are embedded in the adjacent stages for DC-offset cancellation. Implemented in TSMC 65-nm CMOS technology, the proposed PGA exhibits a programmable gain range of 0 dB to 42 dB with 1 dB per step and 0.17 dB error. The gain variation across -40~125 °C is lower than 0.3 dB at all gain settings. The core circuit consumes a DC power of 3.8mV from a 1.2 V supply and occupies a layout area of 0.048 mm2.

This paper presents an automatic amplitude control (AAC) loop voltage controlled oscillator (VCO) with a constant VCO gain (Kvco) for fractional-N frequency synthesizers in WLAN application in 65nm CMOS process. A novel AAC scheme based on a mixed-signal feedback loop has been proposed to minimize the amplitude variation. In order to achieve a low Kvco variation, an extra switched varactor array is also introduced to the LC tank together with the conventional switched capacitor array. The VCO achieves a tuning range of 23.7% from 3.1 to 4.2GHz, while consuming 4.6mA of quiescent current from a 1.2V power supply. The peak amplitude variation over the entire frequency range is less than 10mV, which can be otherwise as large as 100mV, or 22.2% without the AAC loop. The VCO shows a nearly constant Kvco of 60MHz/V, a low phase noise of -123.3dBc/Hz at 1 MHz offset, and a superior FoM of -187dBc/Hz from a 3.6 GHz carrier.

In this paper, a fully integrated 24GHz integer-N PLL for a 60GHz wireless transceiver is presented. A VCO with tail-feedback technique is used to improve the phase noise by modulating the tail current, and a switched varactor array is also adopted together with a switched capacitor array to compensate the variation of KVCOover different bands. Moreover, benefiting from the careful optimization of CML pre-scaling divider, the PLL operates correctly when VCO buffer is turned off, coming up with an extremely low power. The whole PLL is fabricated in standard 90-nm process. Measurement shows that the VCO achieves a phase noise of -102dBc/Hz@1MHz offset with a tuning range of over 16%. The KVCOvariation over all bands is less than 16%. In close-loop operation mode the PLL shows an integrated phase error of 3.3°rms (from 100kHz to 100MHz) over prescribed frequency bands, and a total power dissipation of only 26mW.

A 60GHz receiver for 802.11ad application with superior performance in 90nm CMOS process, compared with prior arts in advanced processes, is proposed and realized. A 3-stage differential LNA achieves a gain of 19.8dB and a noise figure of 6dB in measurement, showing less than 0.3dB difference from simulation due to the elaborate consideration of parasitics. A baseband PGA with wideband and large gain tuning range is achieved from modified Cherry-Hooper amplifier with negative capacitive neutralization technique. The entire receiver achieves a double-side-band NF of 7.1dB and a maximal conversion gain of 64dB with 28dB tuning range, while consuming only 177mW of power. The measured output P1dBis -5.5dBm. All measured results are rigorously loyal to the simulation.

This paper presents a full ESD-protected receiver front-end for wireless communications around 24GHz, comprising LNA, mixer, VGA, and on-chip balun. A π -type input matching network incorporating ESD capacitance is constructed to realize the source impedance transformation for higher gain. With it, the gain of the first stage is improved while the noise figure is just degraded slightly. The measured results show an input return loss of less than-12dB, 36dB voltage gain, 6.9dB noise figure, and 2dBm output P1dB. The chip has an HBM ESD robustness of ± 2kV and consumes 34mA from a 1.2V supply with a total area of 1×0.8 mm2using 0.13μm RF CMOS process.

An analytical framework has been developed to describe the locking behavior of millimeter (mm) wave current mode logic (CML) frequency divider. Unlike traditional analysis based on RC delay, the proposed model is established with injection-locking concept from analog perspective. Both analytical formulas and graphic interpretation are provided for design insights. The model has been validated by exhaustive simulations and important guidelines have been concluded for circuit design.