Nonlinear channel codes are employed to protect two information fields that are related to the daylight saving time (DST) and leap second notifications within the enhanced WWVB broadcast format. The general codebook design criteria and the construction of these codes using integer linear program (ILP) is formulated. Specifically, two different variations are presented: i) minimizing the union bound of probability of word error (PWE), which is a tighter bound but has high computational complexity and ii) minimizing an analytical closed form approximation to the PWE, which has much lower complexity but is a looser bound on the exact PWE. By leveraging the highly non-uniform a-priori probabilities of the different messages being transmitted in these two fields, the proposed nonlinear codes provide coding gains of about 2-3 dB in the presence of additive white Gaussian noise (AWGN). When compared to checksum codes with the same rate, the nonlinear codes offer performance advantages of about 1-2 dB for the DST notification field. In the presence of impulsive noise, simulations and analysis show that the probability of word error when employing the proposed nonlinear code is lower by many orders of magnitude compared with that of the uncoded system.

In this paper, we propose a hypothesis testing based sequential frame synchronization technique that is robust against fluctuations and imperfect estimation of channel gain at the receiver. The proposed detector uses division in the decision rule to cancel the effect of channel gain, and therefore is called division based hypothesis testing (DHT). We show that the receiver operating characteristic (ROC) of DHT is close to the optimal likelihood ratio test (LRT), while the optimal LRT requires perfect knowledge of noise and channel gain at the receiver. Further, we use three performance metrics, namely, the probability of false synchronization Pfs, average reception duration lrx, and probability of missed synchronization Pms, to compare the performance of hypothesis testing against that of point estimation. We analytically show that hypothesis testing can have better reliability and lower energy consumption than point estimation if the probability of false alarm of the hypothesis testing is lower than the minimum of two thresholds. The cost of hypothesis testing is an arbitrarily small Pmswhile point estimation can have zero Pms. A modified implementation of hypothesis testing is also introduced to further reduce the energy consumption.

The architecture and algorithms for the first all-digital radio-controlled clock receiver for the new WWVB broadcast format are proposed. To address the potentially low signal-to-noise ratio conditions and the relatively large frequency offsets experienced in the receiver, two alternative timing synchronization approaches are investigated, i.e., one based on a maximum-likelihood (ML) criterion and the other based on correlation. We show that the correlation-based synchronization technique reduces the implementation complexity by over 50%, while its performance is only less than 1 dB inferior to that of the ML-based technique. Decision and detection algorithms are proposed for two operating regimes in the receiver: tracking and acquisition. In tracking, the proposed decision strategies reduce the timing mean squared error by as much as 63% compared with what the synchronizer produces without any additional processing. In acquisition, the proposed joint synchronization and decoding technique significantly improves the robustness by exploiting the channel code in the data. Compared with receivers based on the legacy broadcast, over 15 dB performance gains are achieved by the modulation and algorithms proposed for the tracking and acquisition operations. In addition to reception performance analyses, energy consumption tradeoffs are also presented.

The performance of digital subscriber line (DSL) systems, such as ADSL and VDSL is limited by crosstalk. Suppression of in-domain far-end self crosstalk using vectoring technology enables very high bidirectional data rates over twisted-pairs of copper wires. However, the performance of vectored DSL systems is severely degraded in the presence of alien or out-of-domain crosstalk that arises from sources that lie outside the vectored DSL system and share the same cable binder. In this paper, we propose a practical, non-iterative, high performance algorithm for alien crosstalk mitigation. Simulation results and complexity analysis corresponding to a vectored VDSL2 system in presence of alien crosstalk are presented to illustrate the significant performance gains of the proposed algorithm and its low implementation complexity.

An optimization scheme is developed for a cosine modulated perfect- reconstruction (PR) filter bank that is tailored to mitigate the effects of narrowband radio frequency interference (RFI). The conventionally used optimization criterion for bandpass filtering is to maximize the sidelobe attenuation by minimizing the stopband energy and minimizing the maximum stopband ripple. The proposed optimization scheme is designed particularly to combat RFI with completely known or partially known statistics. Simulation results for the scenario of strong narrowband RFI show that the proposed optimization scheme offers about 14% data rate improvement in the system's data throughput when compared to the traditional schemes.

Digital sigma-delta (ΣΔ) modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital low-pass ΣΔ modulator, which has lower quantization noise and lower power consumption compared to other recent structures. A conventional digital ΣΔ structure uses a 1-bit quantizer and generates very high quantization noise at higher frequencies. In this work, we present a low-pass digital ΣΔ architecture with a multi-bit quantizer, which achieves very low in-band as well as out-of-band quantization noise levels. It is shown that the structure can be run at half the frequency while meeting the required noise performance and essentially delivering a better power-performance trade-off. The proposed architecture, along with the original 1-bit quantizer structure, has been synthesized in a 90nm CMOS process. Area and power consumption results are presented and a comparison between a commonly used structure and the proposed one is provided.

The digital sigma-delta (ΣΔ) modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital band-pass ΣΔ modulator, running at 900 MHz. The conventional band-pass ΣΔ structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90nm technology using a static CMOS implementation. The loop-unrolling concept was recently presented as a solution for getting required rate of operation. However, this approach requires larger area and consumes higher power. In this work, we present a new architecture to achieve the necessary noise shaping at required rate of operation. The proposed structure has the different Noise Transfer Function (NTF) compared to conventional band-pass structures and hence it gives more control over the location of zeros. It also meets timing requirements of 900 MHz across all PVT corners and shows significant saving in area and power.

A generalized signal reconstruction method is presented for the development of digital FIR interpolation filters, applicable to an analog reconstruction filter impulse response with finite duration that extends to an integer number of the input sampling periods. The technique produces efficient interpolation filter structures for both polynomial and non-polynomial based impulse responses, and could minimize implementation requirements (area, power) for filter designs involving sampling rate conversion.