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Daniel S. Omundsen

dblp:90/1482 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 44% GPUs and heterogeneous computing · 44% Hardware accelerators and domain-specific architectures · 13%
Computer networks
1 paper
Internet architecture and protocols · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols › ISDN
broadband ISDN
0.011994
A pipelined, multiprocessor architecture for a connectionless server for broadband ISDN · IEEE/ACM Trans. Netw. 1994
Processor architecture and microarchitecture
multiprocessor architecture
0.011994
A pipelined, multiprocessor architecture for a connectionless server for broadband ISDN · IEEE/ACM Trans. Netw. 1994
GPUs and heterogeneous computing › packet processing
packet processing pipelines
0.011994
A pipelined, multiprocessor architecture for a connectionless server for broadband ISDN · IEEE/ACM Trans. Netw. 1994
Hardware accelerators and domain-specific architectures
network accelerator
0.011994
A pipelined, multiprocessor architecture for a connectionless server for broadband ISDN · IEEE/ACM Trans. Netw. 1994

Methods — techniques the papers use, named apart from their topics

ATM cell routing · 0.0
YearPublicationVenuePosition
1994 A pipelined, multiprocessor architecture for a connectionless server for broadband ISDN
abstract
The direct provision of connectionless service in BISDN calls for servers that are connected to or are part of an ATM network to provide the routing function at input speeds up to 622 Mb/s. Routing is achieved in such a server by changing the VCI/VPI headers in the ATM cells; actual switching is done by existing switches in the ATM network. The paper presents an architecture capable of executing all the functions of a server at input speeds up to 622 Mb/s, scalable to multiple inputs at that speed, making use of processors and special hardware that are available today. To avoid storing large quantities of data, the architecture routes data packets by examining routing information in the initial cell of the packet and routing subsequent cells as they arrive rather than waiting until the complete packet has arrived. It is capable of handling packets that have been multiplexed at the SAR sublayer using AAL Type 3/4 and, with minor modifications, could also handle Type 5 traffic. Arguments are also presented for the use of AAL Type 5 for the direct connectionless service.>
Daniel S. Omundsen, A. Roger Kaye, Samy A. Mahmoud
IEEE/ACM Trans. Netw.1