Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Mounir Meghelli

dblp:90/1564 · DBLP profile ↗
← Back
2ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.012000
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits · Proc. IEEE 2000
Integrated circuit design
radio-frequency circuit design
0.012000
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits · Proc. IEEE 2000
Integrated circuit design › high-speed integrated circuits › high-speed integrated circuit design
clock and data recovery
0.012000
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits · Proc. IEEE 2000
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
phase-locked loop
0.012000
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits · Proc. IEEE 2000
YearPublicationVenuePosition
2013 A linearized voltage-controlled oscillator for dual-path phase-locked loops
abstract
A voltage-controlled oscillator linearization technique suitable for dual-path phase-locked loops is presented. In the proposed scheme, the state of the integral control path sets the gain of a transconductor in the proportional path in such way that nearly constant VCO gain through the proportional path is achieved. A detailed analysis and design example is presented in the context of delay-interpolating ring-based VCOs. Simulation and measurements in ST 90 nm CMOS technology show that the proposed technique is effective in reducing gain variations across the VCO's tuning range from an uncompensated spread of 1:4 to an average of 1:1.3.
Glenn E. R. Cowan, Mounir Meghelli, Daniel J. Friedman
ISCAS2
2000 Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits
abstract
Over the last decade, SiGe HBT BiCIMOS technology has matured from a laboratory research effort to become a 50/65-GHz fT/fmax silicon-based 0.5-/spl mu/m BiCMOS production technology. This progress has extended silicon-based production technology into the multigigahertz (multi-GHz) and multigigabits-per-second (multi-Gb/s) range, thus, opening up an array of wireless and wired circuit and network applications and markets. SiGe circuits are now being designed in the same application space as GaAs MESFET and HBTs, and offer the yield cost, stability and manufacturing advantages associated with conventional silicon fabrication. A wide range of microwave circuits have been built in this technology including 5.8-GHz low-noise amplifiers with 1-V supply, up to 17-GHz fully monolithic VCOs with excellent figures of merit, high-efficiency 2.4-GHz power devices with supply voltage of 1.5 V, and move complicated functions such as 2.5/5.0-GHz frequency synthesizer circuits as well as 10/12.5-Gb/s clock and data recovery PLLs. This paper focuses on several key circuit applications of SiGe BiCMOS technology and describes the performance improvements that can be obtained by its utilization in mixed-signal microwave circuit design. By way of examples, the article highlights the fact that the combination of high-bandwidth, high-gain and low-noise SiGe HBTs with dense CMOS functionality in a SiGe BiCMOS technology enables implementation of powerful single-chip transceiver architectures for multi-GHz and multi-Gb/s communication applications.
Mehmet Soyuer, Herschel A. Ainspan, Mounir Meghelli, Jean-Olivier Plouchart
Proc. IEEE3