This demo shows a first prototype two-axis miniaturized spiking sun sensor. The device is composed of spiking pixels, and uses a novel Time-to-First-n-Spikes with time-out readout mode to reduce bandwidth consumption and post-processing computation. Due to on-chip processing, and compressing the angle information, the sensor produces much less data and is much faster than digital sensors. Its response latency is 88 μW, and average power consumption is 6.3 μW. An integrated circuit with core electronics was fabricated in the AMS 0.35 μm CMOS image sensor process, and was integrated inside a very small QFN64 package with micro-optics on top.

The paper presents the concept, layout and simulation results for a combined chemical and optical 92×92 pixel array designed as a 3.18×3.18mm2ASIC in standard AMS 0.35μm CMOS technology. The optical pixels employ PN junctions as photodiodes, while the chemical pixels use ISFETs that are pH sensitive with the standard passivation layer of the process. Local light intensity and pH level are encoded using pulse frequency modulation (PFM) and conveyed off-chip using the address event representation (AER) protocol. The chip has been conceived specifically to characterize a light sensitive biomolecular thin film that is in turn intended as a retinal implant for the treatment of end-stage retinal degenerative diseases.

This paper presents an energy efficient inverter based readout circuit for implantable pressure bridge piezo-resistive sensor which can achieve 9 bit resolution with 28.8-mV input voltage range. Only one bridge branch is utilized with interchanging supply voltage to achieve net differential input voltage range, hence reducing the power consumption by a half. A gain compensated technique is applied for inverter based switched capacitor amplifier to achieve both power efficiency and high resolution. A two-step auto calibration is applied to eliminate the offset from non-ideal effects of the switched-capacitor amplifier (SC-amp) and comparator delay. The readout system is implemented and simulated in TSMC 90 nm CMOS technology. With supply voltage of 1.2 V, simulation results show that the circuit can achieve 9.4 bit resolution while consuming only 35 µW during 320 µs conversion time. The digital output code has little sensitivity to temperature variation.

We present a new method to sense NIR (Near Infrared Radiation) with an asynchronous pixel event AER (Address Event Representation) color vision sensor. The sensor's asynchronous output data flow can be processed by a computer to monitor oscillations of NIR illumination levels. Such variations can be indicators for fires or flames. The new sensor is an alternative to high-speed CMOS cameras with NIR filters as front-end for flame detection and characterization methods. Our sensor maintains a high temporal resolution and low latency for regions that are bright in the NIR spectrum, e.g. flames and hot-spots, at an overall low (scene dependent) data rate and power consumption. This makes it specially suitable for Wireless Sensor Networks (WSNs). A dedicated real-time Java interface was programmed to process the sensor outputs. In this paper, we describe the algorithm for sensing NIR intensity and describe experiments that show oscillations of NIR levels of a flame.

Summary form only given. We demonstrate the very first tri-color asynchronous pixel-event vision sensor, the latest addition of the growing family of bio-inspired AER (Address Event Representation) vision sensors. It is an asynchronous pulse/frequency density modulation (PDM/PFM) sensor (popularly known as octopus retina) that employs stacked photo diodes for color separation. Simple linear combination of the sensor's inherent pseudo color representation is employed to reconstruct approximate a RGB video stream. The 22×22 pixel array has been fabricated in the standard STM 90nm CMOS process.

This paper describes a 250-Mb/s to 3Gb/s continuous rate clock and data recovery (CDR) circuit in the TSMC 90nm CMOS process. The circuit first recovers the precise clock frequency from bit-serial 27-1 pseudorandom binary-sequences (PRBS) across a wide range of data rates. Thus, the requirements for loop bandwidth and locking range is much relaxed for the second step of phase detection, implemented as a 1/5 rate linear phase detector (PD) offering reduced clock operating frequency and low jitter. The CDR achieves 12.6-ps peak-to-peak jitter at 2.5Gb/s and consumes a current of 3.84mA in post-layout simulation.

A prototype for a wireless implantable sensor system is demonstrated intended for a pill sized micro-implant for blood sugar monitoring. Power is sent and telemetry data received over a near field inductive link. The implant system is almost completely realized on a single CMOS ASIC, excepting three surface mounted capacitors, the coil antenna and the sensor. For this demonstration, the ASIC is packaged and mounted with the 4 other components on a PCB, and the glucose sensor is substituted with either a potentiometer or an atmospheric pressure sensor. In the targeted highly miniaturized implantable micro system all components (including antenna and sensor) will be integrated into a pill sized LTCC (low temperature cofired ceramics) package. The total implant power budget with the minimal supply voltage of 2.5V is at 76μW. This number includes the power for various test structures that will be unnecessary for an industrial prototype, which is expected to operate below 20μW. A simple demonstrator of the reader is implemented on another PCB with a two digit hexadecimal LED display to show the telemetry data.

We demonstrate one of a new generation of frame-free vision sensors with pixels that convey information asynchronously as a stream of pixel-events. This relatively new paradigm has different advantages and disadvantages which we try to demonstrate with our example sensor.

This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies.

The paper presents a dichromatic asynchronous event pixel for use in an address event representation (AER) vision sensor. The pixel has been produced with the AMS 0.35 mum CMOS process. The sensitivity to two distinct color spectra is achieved by the concept of stacked photo diodes, PN-junctions at different depths below the surface of the silicon chip, which results in different absorption spectra. The pixel emits short pulses at a frequencies proportional to the photo currents of the junctions. The pixel is shown to clearly distinguish light sources of two different colors.

The paper presents a high speed serial address-event representation (AER) link with a capacity of 41.66Mevents/sec. The link has been implemented using a low voltage differential signaling (LVDS) interface on a commercial FPGA. Many of the latest reconfigurable devices (FPGAs, CPLDs, etc.) offer highly optimized modules for this kind of communication. However, many AER processing systems require an ASIC implementation. The paper proposed to implement AER components with a serial AER interface as multi-chip PCBs with one or several ASICs communicating in parallel with an FPGA that handles the external high speed serial link. The authors judge the design effort to be much smaller than in a comparable monolithic ASIC implementation.

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-event- representation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a 2D winner-take-all chip, a delay line chip, a learning classifier chip, and a set of PCBs for computer interfacing and address space remappings. The components use a mixture of analog and digital computation and will learn to classify trajectories of a moving object. A complete experimental setup and measurements results are shown.