Demo Data from SIGIR 2026 / reviewers in the wild / expert
Paul M. Stillwell Jr.
dblp:90/3555
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Internet architecture and protocols · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Internet architecture and protocols › local area network
ethernet |
0.1 | 1 | 2007 | High-performance ethernet-based communications for future multi-core processors · SC 2007 |
Internet architecture and protocols
network interface card |
0.1 | 1 | 2007 | High-performance ethernet-based communications for future multi-core processors · SC 2007 |
Interconnection networks and networks-on-chip
cluster interconnect |
0.0 | 1 | 2007 | High-performance ethernet-based communications for future multi-core processors · SC 2007 |
Methods — techniques the papers use, named apart from their topics
hardware-software co-design · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | High-performance ethernet-based communications for future multi-core processorsabstractData centers and HPC clusters often incorporate specialized networking fabrics to satisfy system requirements. However, Ethernet's low cost and high performance are causing a shift from specialized fabrics toward standard Ethernet. Although Ethernet's low-level performance approaches that of specialized fabrics, the features that these fabrics provide such as reliable in-order delivery and flow control are implemented, in the case of Ethernet, by endpoint hardware and software. Unfortunately, current Ethernet endpoints are either slow (commodity NICs with generic TCP/IP stacks) or costly (offload engines). To address these issues, the JNIC project developed a novel Ethernet endpoint. JNIC's hardware and software were specifically designed for the requirements of high-performance communications within future data-centers and compute clusters. The architecture combines capabilities already seen in advanced network architectures with new innovations to create a comprehensive solution for scalable and high-performance Ethernet. We envision a JNIC architecture that is suitable for most in-data-center communication needs. Mike Schlansker, Bhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi |
SC | 4 |