The scope of most high-level synthesis efforts to date has been at the level of a single behavioral model represented as a control/data-flow graph. The communication between concurrently executing processes and its requirements in terms of timing and resources have largely been neglected. This restriction limits the applicability of most existing approaches for complex system designs. This paper describes a methodology for the synthesis of interfaces in concurrent systems under detailed timing constraints. The authors model interprocess communication using blocking and nonblocking messages. They show how the relationship between messages over time can be abstracted as a constraint graph that can be extracted and used during synthesis. They describe a novel technique called interface matching that minimizes the interface cost by scheduling each process with respect to timing information of other processes communicating with it. By scheduling the completion of operations, some blocking communication can be converted to nonblocking while ensuring the communication remains valid. To further reduce hardware costs, the authors describe the synthesis of interfaces on shared physical media. They show how this sharing can be increased through rescheduling and serialization of the communication. In addition to systematically reducing the interface synchronization cost, this approach permits analysis on the timing consistency of interprocess communication.>

For the synthesis of ASIC design that interface with external signals and events, timing constraints and operations with unbounded delays, i.e. delays unknown at compile time, must be considered. The authors present a relative scheduling formulation that supports operations with fixed and unbounded delays. The start time of an operation is specified in terms of offsets from the set of unbounded delay operations called anchors. The authors analyze a property, called well-posedness, of timing constraints. It is used to identify consistency of constraints in the presence of unbounded delay operations. The authors present an algorithm that will transform an ill-posed constraint graph into a minimally serialized well-posed constraint graph, if one exists. The anchors are then checked for redundancy, and they identify the minimum set of anchors that are required in computing the start time. They present an algorithm that schedules the operations relative to the anchors and yields a minimum schedule that satisfies the timing constraints, or detects whether no schedule exists, in polynomial time. They describe the generation of control logic from the resulting relative schedule.>

Article Free Access Share on Control optimization based on resynchronization of operations Authors: David C. Ku Center for Integrated Systems, Stanford University, Stanford, CA Center for Integrated Systems, Stanford University, Stanford, CAView Profile , Dave Filo Center for Integrated Systems, Stanford University, Stanford, CA Center for Integrated Systems, Stanford University, Stanford, CAView Profile , Giovanni De Micheli Center for Integrated Systems, Stanford University, Stanford, CA Center for Integrated Systems, Stanford University, Stanford, CAView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 366–371https://doi.org/10.1145/127601.127696Published:01 June 1991Publication History 6citation123DownloadsMetricsTotal Citations6Total Downloads123Last 12 Months3Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional scheduling techniques assume fixed execution delays for the operations. For the synthesis of ASIC designs that interface with external signals and events, operations with unbounded delays, i.e. delays unknown at compile time, must also be considered. We present a relative scheduling technique that supports operations with fixed and unbounded delays. The technique satisfies the timing constraints imposed by the user, which places bounds between the activation of operations. We analyze a novel property called well-posedness of timing constraints that is used to identify consistency of constraints in the presence of unbounded delay operations, and present an approach to relative scheduling that yields a minimum schedule that satisfies the constraints, or detects if no schedule exists, in polynomial time.