Due to the increase of required bandwidth, the newer generation of communication systems uses spectrum-efficient digital modulations that involve non-constant envelope RF signals. A technique that potentially can concurrently provide high efficiency and linearity is the Envelope Elimination and Restoration (EER) transmitter architecture which is based on the decomposition of the transmitted signal in a broadband baseband envelope (processed by an envelope-tracking switching power converter) and a narrowband phase-modulated signal (processed by a class-E switch-mode 802.11a WLAN standard RFPA) and the subsequent restoration (through wideband adaptive RF PA supply). In this work, a behavioral system-level characterization of how circuit-level effects (namely limited bandwidth and switching effects) affect the overall communication system performance metrics (characterized by spectra, eye diagrams, signal constellations, EVM and BER) of a 802.11a WLAN system is presented.

Emerging electric-drive vehicles demonstrate the potential for significant reduction of petroleum consumption and greenhouse gas emissions. Existing electric-drive vehicles typi- cally include a battery system consisting of thousands of Lithium-ion battery cells. Therefore, large-scale battery-system modeling and analysis is essential for battery system performance analysis, next-generation battery system design, and transportation electrification.

In this paper, smooth transition between buck and boost modes in 4-switch non-inverting buck-boost power converter is investigated. It is shown, both theoretically and on an experimental converter prototype, how pulse-width modulator (PWM) maximum and minimum duty cycle limitations can result in pulse skipping at the mode transition and substantial increases in the output voltage ripple. This is a very significant problem when the converter is used as a power supply for WCDMA RF power amplifiers. An approach is proposed to achieve smooth mode transition by overlapping buck and boost modes of operation. The approach results in much reduced output voltage ripple, at the expense of reduced efficiency, as demonstrated on the experimental prototype.

The envelope elimination and restoration (EER) technique theoretically allows implementation of linear highly efficient RF power amplifiers, as required for next generation digital communications. One of the key remaining challenges for a successful implementation of the EER technique is the efficient implementation of the switching power converter in charge of amplifying the baseband envelope signal, since bandwidths in the order of several MHz are expected for the envelopes to be tracked, hence requiring very high switching frequencies and thus compromising efficiency. This work investigates the feasibility of the EER technique by studying the impact of the nonidealities associated to the switching power converter, namely its bandwidth and ripple, upon the overall polar amplification EER scheme. Considering a two-tone test input signal, a design space exploration of the distortion associated to both nonideal effects is evaluated in terms of the output spurious-free dynamic range (SFDR). Design criteria for the optimum filtering characteristic and phase compensation between polar paths are derived. The work concludes by exploring the extension of switching power converter design criteria for an actual CDMA modulation signal

PWM buck switching power converters are good candidates for high efficiency power amplification of arbitrary band-limited signals. The correlation between the signal bandwidth and the switching frequency, in turn related to switching losses, imposes practical limits for high bandwidth applications. Stringent specifications appear in such applications as audio amplifiers (kHz signal bandwidths), and lately, in fast envelope tracking power amplifiers (MHz signal bandwidths) for the Envelope Elimination and Restoration technique in polar RF power amplification. Bandwidth limitations in PWM amplifiers are explored in this work by proposing design criteria for obtaining the switching frequency to signal bandwidth ratio (fs/fx) so as to guarantee a given aliasing error. To achieve that purpose, PWM spectra are reviewed for single tone, two-tone and multitone signals. Subsequently, by taking into account the analogy between PWM and FM spectra, bandwidths around the switching frequency are estimated by extending Carson's rule to an arbitrary error. This allows obtaining an extension of the Nyquist criterion for pulse-width modulation. System-level simulation results are reported to validate the analysis, showing that the conventional fs/fxfactor used in the power converter design field might be too conservative

The paper describes a closed-loop controller for adaptive voltage scaling (AVS) where the supply voltage to a standard-cell ASIC is dynamically adjusted to the minimum value required for the desired system speed. The controller includes a clock generator that provides a low-jitter clock to the ASIC at all steady-state operating points and through transients. To speed up the voltage transient response to step changes in clock frequency, the controller is based on a multiple-tap resettable delay line. A chip including the AVS controller and a dual 16-bit MAC application has been fabricated in a standard 0.5 μ CMOS process. The area taken by the AVS controller is 0.12mm2. Experimental results demonstrate operation over the application clock frequency range from 80 kHz to 20 MHz, and a 38μs transient response for a step change in speed from standby to maximum throughput operation.

This paper reviews some of the major approaches to modeling and simulation in power electronics, and provides references that can serve as a starting point for the extensive literature on the subject. The major focus of the paper is on averaged models of various kinds, but sampled-data models are also introduced. The importance of hierarchical modeling and simulation is emphasized.

This paper describes an adaptive power management architecture to reduce power consumption in digital filters. The proposed approach combines two low-power techniques which utilize supply voltage reduction. The first technique, multiple voltage distribution (MVD), attempts to reduce power consumption by assigning reduced supply voltages to circuit modules while satisfying timing constraints. The second technique, adaptive voltage scaling (AVS), dynamically adjusts these multiple voltages to meet throughput requirements resulting in further power reduction. An FIR filter application using the combined MVD-AVS power management scheme for two adaptively scaled supply voltages is shown to consume one-third the power of a fixed supply voltage scheme, and half the power consumed with a single supply AVS.

The design and experimental evaluation of a clocked adiabatic logic (GAL) is described in this paper. CAL is a dual-rail logic that operates from a single-phase AC power-clock supply. This new low-energy logic makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution. CAL can also be operated from a DC power supply in a nonenergy-recovery mode compatible with standard CMOS logic. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in a 1.2 /spl mu/m CMOS technology. Experimental results show that energy savings are achieved at clock frequencies up to about 40 MHz as compared to the nonadiabatic mode. Since CAL can operate both in adiabatic and nonadiabatic modes, power management strategies may be based upon switching between modes when necessary.

In this paper we describe the design and experimental evaluation of a clocked CMOS adiabatic logic (CAL). CAL is a dual-rail logic that operates from a single-phase AC power-clock supply in the 'adiabatic' mode, or from a DC power supply in the 'non-adiabatic' mode. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in 1.2 /spl mu/m technology. Experimental results show energy savings in the adiabatic mode versus the non-adiabatic mode at clock frequencies up to about 40 MHz.