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Bhavana Thudi

dblp:91/1096 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › timing analysis
static timing analysis
0.012003
Non-iterative switching window computation for delay-noise · DAC 2003
Electronic design automation › signal integrity
noise modeling
0.012003
Non-iterative switching window computation for delay-noise · DAC 2003
Electronic design automation
timing analysis
0.012003
Non-iterative switching window computation for delay-noise · DAC 2003

Methods — techniques the papers use, named apart from their topics

superposition · 0.0interval analysis · 0.0
YearPublicationVenuePosition
2003 Non-iterative switching window computation for delay-noise
abstract
In this paper, we present an efficient method for computing switching windows in the presence of delay noise. In static timing analysis, delay noise has traditionally been modeled using a simple switch-factor based noise model and the computation of switching windows is performed using an iterative algorithm, resulting in an overall run time of O(n2), where n is the number of gates in the circuit. It has also been shown that the iterations converge to different solutions, depending on the initial assumptions, making it unclear which solution is correct. In this paper, we show that the iterative nature of the problem is due to the switching-factor based noise model and the order in which events are evaluated. We utilize a delay noise model based on superposition and propose a new algorithm with a run time that is linear with the circuit size. Since the algorithm is non iterative and does not operate with initial assumptions, it also eliminates the multiple solution problem. We tested the algorithm on a number of designs and show that it achieves significant speedup over the iterative approach.
Bhavana Thudi, David T. Blaauw
DAC1