We present a novel distributed scheduling paradigm for Internet routers with input-queued (IQ) switches, called cooperative token-ring (CTR) that provides significant performance improvement over existing scheduling schemes with comparable complexity. Many classical schedulers for IQ switches employ round-robin arbiters, which can be viewed as non-cooperative token-rings, where a separate token is used to resolve contention for each shared resource (e.g., an output port) and each input port acquires a token oblivious of the state of other input ports. Although classical round-robin scheduling schemes achieve fairness and high throughput for uniform traffic, under non-uniform traffic the performance degrades significantly. We show that by using a simple cooperative mechanism between the otherwise non-cooperative arbiters, the performance can be significantly improved. The CTR scheduler dynamically adapts to non-uniform traffic patterns and achieves essentially 100% throughput. The proposed cooperative mechanism is conceptually simple and is supported by experimental results. To provide adequate support for rate guarantees in IQ switches, we present a weighted cooperative token-ring, a simple hierarchical scheduling mechanism. Finally, we analyze the hardware complexity introduced by the cooperative mechanism and describe an optimal hardware implementation for an N times N switch with time complexity of Theta(log N) and circuit size of Theta(N log N) per port.

The integration of thousands of optical input/output (I/O) devices and large electronic crossbar switching elements onto a single optoelectronic integrated circuit (IC) can place stringent power demands on the CMOS substrates. Currently, there is no sufficiently general analytic methodology for power analysis and power reduction of large-scale crossbar switching systems. An analysis of the power complexity of single-chip optoelectronic switches is presented, assuming the classic broadcast-and-select crossbar architecture. The analysis yields the distribution of power dissipation and allows for design optimization. Both unpipelined and pipelined designs are analyzed, and a technique to reduce power dissipation significantly is proposed. The design of a 5.12 Tbit single-chip optoelectronic switch using 0.18-/spl mu/m CMOS technology is illustrated. The pipelined switch design occupies < 70 mm/sup 2/ of CMOS area, and consumes <80 W of power, which compares favorably to the power required in electrical crossbar switches of equivalent capacity.

We present a novel scheduling algorithm for Internet routers with input-queued switches based on credit-based fair queueing. We present a flow-based iterative credit-based fair scheduler (iCBFS) for crossbar switches, that provides fair bandwidth distribution among flows at a fine granularity and achieves asymptotically 100% throughput, under uniform traffic. To reduce the implementation complexity of iCBFS, we present a port-based version of iCBFS that is tailored towards high-speed hardware implementation.

Optoelectronic integrated circuits can support thousands of integrated optical laser diodes and photodetectors bonded to a high-performance CMOS substrate, and can be used in the design of multi-Terabit optical local area networks. This paper describes the design of an integrated optoelectronic CMOS crossbar switch to interconnect approx. 128 parallel fiber ribbon optical links, each with 12 channels clocked at 2.5 Gigabit/sec, to achieve a local area network (LAN) with an aggregate capacity of 3.84 Terabits/second. A prototype switch core has been designed in 0.18 /spl mu/m CMOS technology. Logic optimization and synthesis was performed using the synopsis logic optimization tools, and VLSI layout was performed using the Cadence 2002 tools. It is shown that using 0.18 /spl mu/m CMOS technology, a 3.84 Terabit crossbar switch for an optoelectronic LAN occupies approx. 1.78 sq. cm of real estate, and consumes approx. 90 watts of power.