An I/sub DDQ/ test method is proposed in this paper, which is applicable even if supply current measurement is impaired by noise. Wavelet transformation is used for noise elimination in the test method. In this paper, it is shown by some experiments that bridging faults will be detected by using the proposed test method. Since expert knowledge on filter design is not needed in noise elimination of the I/sub DDQ/ test method, it is expected that the test method will be used in many I/sub DDQ/ tests.

In this paper, an I/sub DDQ/ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for I/sub DDQ/ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that I/sub DDQ/ test time can be reduced by using this test circuit.

In this paper, test time reduction for I/sub DDQ/ testing is discussed. Although I/sub DDQ/ testing is known to be effective in detecting faults in CMOS circuits, the test time of I/sub DDQ/ testing is larger than that of logic testing. It is shown that the test time of I/sub DDQ/ test mostly depends on the switching current. To reduce the test time of I/sub DDQ/ testing, a procedure to arrange test vectors such that the switching current quickly disappears is proposed for combinational circuits. The procedure utilizes a unit delay model to estimate the time of the last transition of logic values from low to high in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.

In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable supply voltage and electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results show that, by using the method, open defects in CMOS ICs can be detected. Also, the test input vectors for the test method are proposed and it is shown that they can be generated more easily than functional test methods based on stuck-at fault models.

In this paper, a procedure to reduce sequential circuits by removing undetectable faults in sequential circuits is proposed. To identify whether an undetectable fault is removable or not, strongly unreachable states, which are the states with no incoming transitions, are utilized. It is proved that part of undetectable faults related to strongly unreachable states can be removed from a circuit. Test generation method is used to find undetectable faults related to two or more strongly, unreachable states. Experimental results for ISCAS benchmark circuits are shown.

In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results promised that, by using the method, open defects in CMOS ICs can be detected by measuring supply current which flows when time-variable electric field is applied.

A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.

When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may be generated in the circuit. In this paper, the necessary conditions are presented for feedback bridging faults to generate logical oscillation. Also, a method is proposed to identify such faults in feedback bridging ones. It is based on piecewise-linearized models obtained from input/output characteristics of logic gates and does not require circuit simulation of large size of circuits to identify them. In the experiments for evaluating the method, all of the feedback bridging faults to generate logical oscillation are identified by using the method.

A new high speed Built-In Current (BIC) sensor is proposed, which is applicable for I/sub DDQ/ tests of low power ICs. The layout of the sensor is designed with CMOS 1.2 /spl mu/m technology. By using this sensor, resistive bridging faults in a circuit, whose supply voltage is 3.3 V, can be detected at the test speed of 66.7 MHz.

A practical supply current test method is proposed and the experimental evaluation results are presented. In the method, the unit-to-unit variation of electrical characteristics in each logic gate is modeled as a Gaussian distribution and faults are detected with a statistical hypothesis technique.

In this paper, an algorithmic test generation method for supply current testing of TTL combinational circuits is proposed. In this method, primary input assignment like in PODEM is used for sensitizing a fault and generating the fault effect on supply current of a circuit under test. Test input vectors for ISCAS-85 benchmark circuits are derived by a random method and the proposed algorithmic method. The test generation results show that with the algorithmic method, test input vectors of faults, whose test vectors can not be derived with the random method, can be derived.

In this paper, derivation problems of maximum cliques are discussed, which take place in simplification processes of incompletely specified machines. In many cases, graphs consisting of a lot of edges are generated in the processes. Thus, for many combinations of the edges, it should be examined whether a clique is made of them. Therefore, it is impossible to derive the maximum cliques within a reasonable time. This paper presents a new algorithm to derive all the maximum cliques, which is more suitable for the derivation of maximum cliques of the undirected graphs generated in the simplification processes.>

The adjustment problem of circuit parameters in analog circuits is formalized as a fuzzy mathematical programming problem, and a novel method is proposed to derive the acceptable parameters that satisfy the designer's requests, each of which is specified by a membership function and the permissible minimum satisfactory level. The search direction to adjust the parameters is determined by using a rule base in which the expert knowledge to improve the performance of the circuit is stored. The search step is determined by the golden selection method. The effectiveness of this method is checked by some experiments for the mu A709 operational amplifier circuit. From these experiments, it is found out that (1) it is useful to evaluate how much the circuit can satisfy the designer's requests at the satisfactory level, and (2) this method can derive a solution with the maximum satisfactory level even if there are trade-off relations between satisfactions.>

A fault detection technique is proposed which can detect logical faults in combinational circuits by measuring the supply current instead of the output logic, and the effectiveness is evaluated by experiments of the circuits made of TTL (transistors-transistor logic) ICs. This technique is based on the assumption that the supply current will be changed by faults in the logic circuits. A generation mechanism of current variation is represented by an autoregressive model, and faults are detected by using pattern-recognition methods.>

This correspondence investigates a model of description for sequential systems having state-transitions among any number of stable states, quasi-stable states, and unstable states. The quasi-stable states are typically seen in the so-called astable and monostable multivibrators in pulse circuits.